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1 of 117 072401 features complete e1 (cept) pcm-30/isdn-pri transceiver functionality onboard long and short haul line interface for clock/data recovery and waveshaping 32-bit or 128-bit crysta l-less jitter attenuator frames to fas, cas, ccs, and crc4 formats integral hdlc controller with 64-byte buffers configurable for sa bits, ds0 or sub ds0 operation dual two?frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192mhz interleaving pcm bus operation 8?bit parallel control por t that can be used directly on either multiplexed or non? multiplexed buses (intel or motorola) extracts and inserts cas signaling detects and generates remote and ais alarms programmable output clocks for fractional e1, h0, and h12 applications fully independent transmit and receive functionality full access to si and sa bits aligned with crc-4 multiframe four separate loopback functions for testing functions large counters for bipolar and code violations, crc4 code word errors, fas word errors, and e bits ieee 1149.1 jtag-boundary scan architecture pin compatible with ds2154/52/352/552 scts 3.3v (ds21354) or 5v (DS21554) supply; low power cmos 100-pin lqfp package (14mm x 14mm) ordering information ds21354l (0 0 c to 70 0 c) ds21354ln (-40 0 c to +85 0 c) DS21554l (0 0 c to 70 0 c) DS21554ln (-40 0 c to +85 0 c) description the ds21354/554 single-chip transceiver (sct) contains all of the necessary functions for connection to e1 lines. the device is an upward compatible version of the ds2153 and ds2154 scts. the onboard clock/data recovery circuitry coverts the ami/hdb3 e1 waveforms to an nrz serial stream. the ds21354/554 automatically adjusts to e1 22awg (0.6 mm) twisted?pair cables from 0 to over 2km in length. the device can generate the necessary g.703 waveshapes for both 75 ohm coax and 120 ohm twisted cables. the onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. the framer locates the frame and multiframe boundaries and monito rs the data stream for alarms. it is also used for extracting and inserting signaling data, si, and sa bit information. the onboard hdlc controller can be used for sa bit links or ds0s. the device contains a set of internal registers which the user can access and control the operation of the unit. quick access via the parallel control port allows a single controller to handle many e1 lines. the device fully meets all of the latest e1 specifications including itu-t g.703, g.704, g.706, g.823, g.732, and i.431, ets 300 011, 300 233, and 300 166, as well as ctr12 and ctr4. ds21354 (3.3v) and DS21554 (5v) e1 single chip transceivers (sct) www.maxim-ic.com 1 100
ds21354 & DS21554 2 of 117 table of contents 1 list of figures ............................................................................................................... ........5 2 list of tables................................................................................................................ .........6 3 introduction .................................................................................................................. .......7 3.1 functional description...................................................................................................... .........8 3.2 document revision history................................................................................................... ....9 4 pin description............................................................................................................... .....11 4.1 pin function description .................................................................................................... .....15 4.1.1 transmit side pins ........................................................................................................ .15 4.1.2 receive side pins......................................................................................................... ..18 4.1.3 parallel control port pins...............................................................................................2 0 4.1.4 jtag test access port pins ..........................................................................................22 4.1.5 interleave bus operation pins........................................................................................23 4.1.6 line inte rface pins ....................................................................................................... ..23 4.1.7 supply pins............................................................................................................... ......24 5 parallel port ................................................................................................................. ....24 5.1 register map................................................................................................................ ............25 6 control, id, and test registers...............................................................................29 6.1 power-up sequence........................................................................................................... ......30 6.1.1 synchronizatrion and re-synchronization .....................................................................31 6.2 framer loopback............................................................................................................. ........34 6.3 automatic alarm generation.................................................................................................. .35 6.4 remote loopback ............................................................................................................. .......37 6.5 local loopback .............................................................................................................. .........34 7 status and information registers .......................................................................39 7.1 crc4 sync counter........................................................................................................... ......41 8 error count registers..................................................................................................44 8.1 bpv or code violation counter..............................................................................................4 4 8.2 crc4 error counter .......................................................................................................... ......45 8.3 e-bit counter............................................................................................................... ............45 8.4 fas error counter........................................................................................................... ........46 9 ds0 monitoring function .............................................................................................46
ds21354 & DS21554 3 of 117 10 signaling operation .......................................................................................................48 10.1 processor based signaling.................................................................................................. ...........48 10.2 hardware based signaling................................................................................................... ....51 10.2.1 receive side............................................................................................................. ......51 10.2.2 transmit side ............................................................................................................ .....51 11 per-channel code generation and loopback................................................52 11.1 transmit side code generation.............................................................................................. .52 11.1.1 simple idle code inser tion and per-channel loopback................................................52 11.1.2 per-channel code insertion ...........................................................................................53 11.2 receive side code generation ............................................................................................... .54 12 clock blocking registers..........................................................................................54 13 elastic stores operation............................................................................................56 13.1 receive side ............................................................................................................... .............56 13.2 transmit side.............................................................................................................. .............56 14 additional (sa) and internatio nal (si) bit operation ...............................56 14.1 hardware scheme ............................................................................................................ ........57 14.2 internal register scheme based on double-frame.................................................................57 14.3 internal register scheme based on crc4 multiframe ...........................................................59 15 hdlc controller for the sa bits or ds0 ............................................................60 15.1 general overview ........................................................................................................... .........60 15.2 hdlc status registers...................................................................................................... ......61 15.3 basic operation details .................................................................................................... .......62 15.3.1 receive a hdlc message .............................................................................................62 15.3.2 transmit an hdlc message..........................................................................................62 15.4 hdlc register description .................................................................................................. ..63 16 line interface functions ............................................................................................68 16.1 receive clock and data recovery ..........................................................................................69 16.2 transmit waveshaping and line driving................................................................................69 16.3 jitter attenuator .......................................................................................................... .............71 16.4 protected interfaces....................................................................................................... ...........74 16.5 receive monitor mode ....................................................................................................... .....76 17 jtag-voundary scan architecture and test access port.....................77 17.1 description................................................................................................................ ...............77 17.2 tap controller state machine ............................................................................................... .78 17.3 instruction register....................................................................................................... ...........81 17.4 test registers............................................................................................................. ..............83
ds21354 & DS21554 4 of 117 18 interleaved pcm bus operation..............................................................................86 18.1 channel interleave ......................................................................................................... ..........87 18.2 frame interleave ........................................................................................................... ...........87 19 functional timing diagrams.....................................................................................88 19.1 receive.................................................................................................................... .................88 19.2 transmit ................................................................................................................... ................94 20 operating parameters ................................................................................................103 21 ac timing parameters and diagrams .................................................................104 21.1 multiplexed bus ac characteristics .....................................................................................104 21.2 non-multiplexed bus ac characteristics .............................................................................107 21.3 receive side ac characteristics ...........................................................................................1 10 21.4 transmit ac characteristics................................................................................................ ..114 22 mechanical description ............................................................................................117
ds21354 & DS21554 5 of 117 1 list of figures figure 3-1 ds2135/554 block diagram.................................................................................10 figure 16-1 basic externa l analog connections.......................................................71 figure 16-2 optional crystal connection......................................................................72 figure 16-3 jitter tolerance ..................................................................................................72 figure 16-4 jitter attenuation .............................................................................................73 figure 16-5 transmit waveform template .....................................................................73 figure 16-6 protected interface example for the DS21554 ....................................74 figure 16-7 protected interface example for the ds21354 ....................................75 figure 16-8 typical monitor port application.............................................................76 figure 17-1 jtag functi onal block diagram.................................................................78 figure 17-2 tap controller state diagram ...................................................................81 figure 18-1 ibo basic configuration using 4 scts .......................................................87 figure 19-1 receive side timing..............................................................................................88 figure 19-2 receive side boundary timi ng (with elastic store disabled).........................89 figure 19-3 receive side 1.544 mhz boundary timing (with elastic store enabled) ......90 figure 19-4 receive side 2.048 mhz boundary timing (with elastic store enabled) .....91 figure 19-5 receive side interleave bus operation, byte mode .........................92 figure 19-6 receive side interleave bus operation, frame mode ......................93 figure 19-7 transmit side timing ..........................................................................................94 figure 19-8 transmit side boundary timi ng (with elastic store disabled) .....................95 figure 19-9 transmit side 1.544 mhz boundary timing (with elastic store enabled) ..........96 figure 19-10 transmit side 2.048 mhz boundary timing (with elastic store enabled) ..........97 figure 19-11 transmit side interleav e bus operations, byte mode....................98 figure 19-12 transmit side interleav e bus operations, frame mode ................99 figure 19-13 g.802 timing ....................................................................................................... .....100 figure 19-14 ds21354/554 framer s ynchronization flowchart .............................101 figure 19-15 ds21354/554 transmit data flow..................................................................102 figure 21-1 intel bus read ac timing (bts=0 / mux=1)................................................105 figure 21-2 intel bus write timing (bts=0 / mux=1) ...................................................105 figure 21-3 motorola bus ac timing (bts=1 / mux=1) ................................................106 figure 21-4 intel bus read ac timing (bts=0 / mux=0)................................................108 figure 21-5 intel bus write ac timing (bts=0 / mux=0)..............................................108 figure 21-6 motorola bus read ac timing (bts=1 / mux=0).....................................109 figure 21-7 motorola bus write ac timing (bts=1 / mux=0)...................................109 figure 21-8 receive side ac timing .....................................................................................111 figure 21-9 receive system side ac timing ....................................................................112 figure 21-10 receive line interface ac timing..............................................................113 figure 21-11 transmit side ac timing .................................................................................115 figure 21-12 transmit system side ac timing.................................................................116 figure 21-13 transmit line interface side ac timing ................................................116
ds21354 & DS21554 6 of 117 2 list of tables table 4-1 pin description sorted by pin number......................................................11 table 4-2 pin description by symbol ..............................................................................13 table 5-1 register map sorted by address.................................................................25 table 6-1 device id bit map...................................................................................................29 table 6-2 sync/resync criteria.........................................................................................31 table 7-1 alarm criteria......................................................................................................42 table 15-1 hdlc controller register list....................................................................61 table 16-1 line build out select in licr for the DS21554........................................70 table 16-2 line build out select in licr for the ds21354........................................70 table 16-3 transformer specifications .........................................................................70 table 16-4 receive monitor mode gain ...........................................................................76 table 17-1 instruction codes for ieee 1149.1 architecture .................................81 table 17-2 id code structure ...............................................................................................82 table 17-3 devic e id codes...................................................................................................... 82 table 17-4 boundary scan control bits........................................................................83 table 18-1 ibo master device select ................................................................................86
ds21354 & DS21554 7 of 117 3 introduction the ds21354/554 is a superset version of the popular ds2153 and ds2154 scts offering the new features listed below. all of the original feat ures of the ds2153 and ds2154 have been retained and software created for the original devi ces is transferable into the ds21354/554. new features in the ds21354 and DS21554 feature section hdlc controller with 64-byte buffers for sa bits or ds0s or sub ds0s 15 interleaving pcm bus operation 18 ieee 1149.1 jtag-boundary scan architecture 17 3.3v (ds21354 only) supply 2 and 3 line interface support for the g.703 2.048 synchronization interface 16 customer disconnect indication (...101010...) generator 6 open drain line driver option 16 new features in the ds2154 (also in the ds21354 and DS21554) feature section option for non?multiplexed bus operation 1 and 2 crystal?less jitter attenuation 12 additional hardware signaling capability including: receive signaling reinsertion to a backplane multiframe sync availability of signaling in a separate pcm data stream signaling freezing interrupt genera ted on change of signaling data 7 improved receive sensitivity: 0 db to ?43 db 12 per?channel code insertion in both transmit and receive paths 8 expanded access to sa and si bits 11 rcl, rlos, rra, and rais alarms now interrupt on change of state 4 8.192 mhz clock synthesizer 1 per?channel loopback 8 addition of hardware pins to indicate carrier loss and signaling freeze 1 line interface function can be completely decoupled from the framer/formatter to allow: interface to optical, hdsl, and other nrz interfaces ?tap? the transmit and receive bipolar data streams for monitoring purposes be able to corrupt data and insert framing errors, crc errors, etc. 1 transmit and receive elastic stores now have independent backplane clocks 1 ability to monitor one ds0 channel in both the transmit and receive paths 6 access to the data streams in between the framer/formatter and the elastic stores 1 ais generation in the line interface that is independent of loopbacks 1 and 3 transmit current limiter to meet the 50 ma short circuit requirement 12 option to extend carrier loss criteria to a 1 ms period as per ets 300 233 3 automatic rai generation to ets 300 011 specifications 3
ds21354 & DS21554 8 of 117 3.1 functional description the analog ami/hdb3 waveform off of the e1 line is transformer coupled into the rring and rtip pins of the ds21354/554. the device r ecovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the dig ital serial stream is analyzed to locate the framing/multi-frame pattern. the ds21354/554 c ontains an active filter that reconstructs the analog received signal for the nonlinear losses that o ccur in transmission. the device has a usable receive sensitivity of 0 db to ?43 db which allows the devi ce to operate on cables over 2km in length. the receive side framer locates fas frame and crc and cas multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of sync hronization, ais and remote alarm. if needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered e1 data stream and an asynchronous backplane clock which is provided at the rsysclk input. the clock applied at th e rsysclk input can be either a 2.048/4.096/8.192 mhz clock or a 1.544 mhz clock. the transmit side framer is totally independent from the receive side in both the clock requirements and characteristics. data off of a backplane can be passed through a transmit side elastic store if necessary. the transmit formatter will provide the necessary frame/multiframe data overhead for e1 transmission. reader?s note: this data sheet assumes a particular nomen clature of the e1 operating environment. in each 125 us frame, there are 32 eight?bit timeslots num bered 0 to 31. timeslot 0 is transmitted first and received first. these 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on. each timeslot (or channel) is made up of eight bits which are numbered 1 to 8. bit number 1 is the msb and is transmitted first. bit number 8 is the lsb and is transmitted last. the term ?locked? is used to refer to two clock signals that are phase or frequency locked or derived from a common clock (i.e., a 1.544mhz clock may be locked to a 2.048mhz clock if they share the same 8khz component). throughout this data sheet, the following abbreviations will be used: fas frame alignment signal cas channel associated signaling mf multiframe si international bits crc4 cyclical redundancy check ccs common channel signaling sa additional bits e-bit crc4 error bits
ds21354 & DS21554 9 of 117 3.2 document revision history date notes 1-27-99 initial release 1-28-99 corrected tsyscl k and rsysclk timing and added 4.096 mhz and 8.192 mhz timing 2-3-99 corrected definition and label of tudr bit in the thir register. 2-11-99 correct address of ibo register in text. 4-1-99 add receive monitor mode section 4-15-99 add section on protected interfaces 5-7-99 correct pin # and descri ption of fms in jtag section 7-29-99 add list of tables and figures 9-14-99 add 10uf cap to interface examples 9-23-99 correct definition of ds* in pin description.
ds21354 & DS21554 10 of 117 ds21354/554 block diagram figure 3-1 receive side framer transmit side formatter elastic store tsync tclk tchclk tser tchblk rchclk rchblk rmsync tssync tsysclk rser rsysclk rsync rfsync tlink tlclk timing control elastic store sync control timing control rlos/lotc signaling buffer hardware signaling insertion tsig rsigf rcl local loopback tring ttip jitter attenuator either transmit or receive path receive line i/f clock / data recovery rring rtip remote loopback vco / pll mclk 8xclk 8mclk 8.192mhz clock synthesizer 32.768mhz 16.384 mhz xtald rclk rposo rnego rnegi rposi tposi tnegi tnego tposo teso tdata rclko rclki rdata tclki tclko liuc liuc parallel & test control port (routed to all blocks) d0 to d7 / ad0 to ad7 bts int* wr*(r/w*) rd*(ds*) cs* test ale(as) / a7 a0 to a6 mux 8 7 interleave bus ci rsysclk interleave bus mux mux t r a n s m i t l i n e i / f data clock sync framer loopback hdlc/boc controller sa / ds0 lotc mux hdlc/boc controller sa / ds0 sync clock data co jtag port j r s t * jtms jtclk jtdi jtdo rlink rlclk rsig sa
ds21354 & DS21554 11 of 117 4 pin description pin description sorted by pin number table 4-1 pin symbol type description 1 rchblk o receive channel block 2 jtms i ieee 1149.1 test mode select 3 8mclk o 8.192 mhz clock 4 jtclk i ieee 1149.1 test clock signal 5 jtrst* i ieee 1149.1 test reset 6 rcl o receive carrier loss 7 jtdi i ieee 1149.1 test data input 8 nc ? no connect (do not connect any signal to this pin) 9 nc ? no connect (do not connect any signal to this pin) 10 jtdo o ieee 1149.1 test data output 11 bts i bus type select 12 liuc i line interface connect 13 8xclk o eight times clock 14 test i test 15 nc ? no connect (do not connect any signal to this pin) 16 rtip i receive analog tip input 17 rring i receive analog ring input 18 rvdd ? receive analog positive supply 19 rvss ? receive analog signal ground 20 rvss ? receive analog signal ground 21 mclk i master clock input 22 xtald o quartz crystal driver 23 nc ? no connect 24 rvss ? receive analog signal ground 25 int* o interrupt 26 nc ? no connect (do not connect any signal to this pin) 27 nc ? no connect (do not connect any signal to this pin) 28 nc ? no connect (do not connect any signal to this pin) 29 ttip o transmit analog tip output 30 tvss ? transmit analog signal ground 31 tvdd ? transmit analog positive supply 32 tring o transmit analog ring output 33 tchblk o transmit channel block 34 tlclk o transmit link clock 35 tlink i transmit link data 36 ci i carry in 37 tsync i/o transmit sync 38 tposi i transmit positive data input 39 tnegi i transmit negative data input 40 tclki i transmit clock input 41 tclko o transmit clock output 42 tnego o transmit negative data output 43 tposo o transmit positive data output
ds21354 & DS21554 12 of 117 pin symbol type description 44 dvdd ? digital positive supply 45 dvss ? digital signal ground 46 tclk i transmit clock 47 tser i transmit serial data 48 tsig i transmit signaling input 49 teso o transmit elastic store output 50 tdata i transmit data 51 tsysclk i transmit system clock 52 tssync i transmit system sync 53 tchclk o transmit channel clock 54 co o carry out 55 mux i bus operation 56 d0/ad0 i/o data bus bit0/ address/data bus bit 0 57 d1/ad1 i/o data bus bit1/ address/data bus bit 1 58 d2/ad2 i/o data bus bit 2/address/data bus 2 59 d3/ad3 i/o data bus bit 3/address/data bus bit 3 60 dvss ? digital signal ground 61 dvdd ? digital positive supply 62 d4/ad4 i/o data bus bit4/address/data bus bit 4 63 d5/ad5 i/o data bus bit 5/address/data bus bit 5 64 d6/ad6 i/o data bus bit 6/address/data bus bit 6 65 d7/ad7 i/o data bus bit 7/address/data bus bit 7 66 a0 i address bus bit 0 67 a1 i address bus bit 1 68 a2 i address bus bit 2 69 a3 i address bus bit 3 70 a4 i address bus bit 4 71 a5 i address bus bit 5 72 a6 i address bus bit 6 73 ale(as)/a7 i address latch enable /address bus bit 7 74 rd*(ds*) i read input(data strobe) 75 cs* i chip select 76 fms i framer mode select 77 wr*(r/w*) i write input(read/write) 78 rlink o receive link data 79 rlclk o receive link clock 80 dvss ? digital signal ground 81 dvdd ? digital positive supply 82 rclk o receive clock 83 dvdd ? digital positive supply 84 dvss ? digital signal ground 85 rdata o receive data 86 rposi i receive positive data input 87 rnegi i receive negative data input 88 rclki i receive clock input 89 rclko o receive clock output
ds21354 & DS21554 13 of 117 pin symbol type description 90 rnego o receive negative data output 91 rposo o receive positive data output 92 rchclk o receive channel clock 93 rsigf o receive signaling freeze output 94 rsig o receive signaling output 95 rser o receive serial data 96 rmsync o receive multiframe sync 97 rfsync o receive frame sync 98 rsync i/o receive sync 99 rlos/lotc o receive loss of sync/ loss of transmit clock 100 rsysclk i receive system clock pin description by symbol table 4-2 pin symbol type description 3 8mclk o 8.192 mhz clock 13 8xclk o eight times clock 66 a0 i address bus bit 0 67 a1 i address bus bit 1 68 a2 i address bus bit 2 69 a3 i address bus bit 3 70 a4 i address bus bit 4 71 a5 i address bus bit 5 72 a6 i address bus bit 6 73 ale(as)/a7 i address latch enable/ address bus bit 7 11 bts i bus type select 36 ci i carry in 54 co o carry out 75 cs* i chip select 56 d0/ad0 i/o data bus bit0/ address/data bus bit 0 57 d1/ad1 i/o data bus bit1/ address/data bus bit 1 58 d2/ad2 i/o data bus bit 2/address/data bus 2 59 d3/ad3 i/o data bus bit 3/address/data bus bit 3 62 d4/ad4 i/o data bus bit4/address/data bus bit 4 63 d5/ad5 i/o data bus bit 5/address/data bus bit 5 64 d6/ad6 i/o data bus bit 6/address/data bus bit 6 65 d7/ad7 i/o data bus bit 7/address/data bus bit 7 44 dvdd ? digital positive supply 81 dvdd ? digital positive supply 61 dvdd ? digital positive supply 83 dvdd ? digital positive supply 45 dvss ? digital signal ground 60 dvss ? digital signal ground 80 dvss ? digital signal ground 84 dvss ? digital signal ground 76 fms i framer mode select 25 int* o interrupt
ds21354 & DS21554 14 of 117 pin symbol type description 4 jtclk i ieee 1149.1 test clock signal 7 jtdi i ieee 1149.1 test data input 10 jtdo o ieee 1149.1 test data output 2 jtms i ieee 1149.1 test mode select 5 jtrst* i ieee 1149.1 test reset 12 liuc i line interface connect 21 mclk i master clock input 55 mux i bus operation 8 nc ? no connect (do not connect any signal to this pin) 9 nc ? no connect (do not connect any signal to this pin) 15 nc ? no connect (do not connect any signal to this pin) 23 nc ? no connect (do not connect any signal to this pin) 26 nc ? no connect (do not connect any signal to this pin) 27 nc ? no connect (do not connect any signal to this pin) 28 nc ? no connect (do not connect any signal to this pin) 1 rchblk o receive channel block 92 rchclk o receive channel clock 6 rcl o receive carrier loss 82 rclk o receive clock 88 rclki i receive clock input 89 rclko o receive clock output 74 rd*(ds*) i read input(data strobe) 85 rdata o receive data 97 rfsync o receive frame sync 79 rlclk o receive link clock 78 rlink o receive link data 99 rlos/lotc o receive loss of sync/ loss of transmit clock 96 rmsync o receive multiframe sync 87 rnegi i receive negative data input 90 rnego o receive negative data output 86 rposi i receive positive data input 91 rposo o receive positive data output 17 rring i receive analog ring input 95 rser o receive serial data 94 rsig o receive signaling output 93 rsigf o receive signaling freeze output 98 rsync i/o receive sync 100 rsysclk i receive system clock 16 rtip i receive analog tip input 18 rvdd ? receive analog positive supply 19 rvss ? receive analog signal ground 20 rvss ? receive analog signal ground 24 rvss ? receive analog signal ground 33 tchblk o transmit channel block 53 tchclk o transmit channel clock 46 tclk i transmit clock
ds21354 & DS21554 15 of 117 pin symbol type description 40 tclki i transmit clock input 41 tclko o transmit clock output 50 tdata i transmit data 49 teso o transmit elastic store output 14 test i test 34 tlclk o transmit link clock 35 tlink i transmit link data 39 tnegi i transmit negative data input 42 tnego o transmit negative data output 38 tposi i transmit positive data input 43 tposo o transmit positive data output 32 tring o transmit analog ring output 47 tser i transmit serial data 48 tsig i transmit signaling input 52 tssync i transmit system sync 37 tsync i/o transmit sync 51 tsysclk i transmit system clock 29 ttip o transmit analog tip output 31 tvdd ? transmit analog positive supply 30 tvss ? transmit analog signal ground 77 wr*(r/w*) i write input(read/write) 22 xtald o quartz crystal driver 4.1 pin function description 4.1.1 transmit side pins signal name: tclk signal description: transmit clock signal type: input a 2.048 mhz primary clock. used to clock da ta through the transmit side formatter. signal name: tser signal description: transmit serial data signal type: input transmit nrz serial data. sampled on the falling edge of tclk when the transmit side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit side elastic store is enabled. signal name: tchclk signal description: transmit channel clock signal type: output a 256 khz clock which pulses high during the lsb of each channel. synchronous with tclk when the transmit side elastic store is disa bled. synchronous with tsysclk when the transmit side elastic store is enabled. useful for parallel to se rial conversion of channel data.
ds21354 & DS21554 16 of 117 signal name: tchblk signal description: transmit channel block signal type: output a user programmable output that can be forced hi gh or low during any of the 32 e1 channels. synchronous with tclk when the transmit side elas tic store is disabled. synchronous with tsysclk when the transmit side elastic store is enabled. useful for blocking clocks to a serial uart or lapd controller in applications where not all e1 channe ls are used such as fractional e1, 384 kbps (h0), 768 kbps or isdn?pri . also useful for locating indi vidual channels in drop?and?i nsert applications, for external per?channel loopback, and for per?cha nnel conditioning. see section 12 for details. signal name: tsysclk signal description: transmit system clock signal type: input 1.544 mhz , 2.048 mhz , 4.096 mhz or 8.192 mhz clock. only used when the transmit side elastic store function is enabled. should be tie d low in applications that do not use the transmit side elastic store. see section 18 on page 86 for details on 4.096 mhz and 8.192 mhz operation using the interleave bus option. signal name: tlclk signal description: transmit link clock signal type: output 4 khz to 20 khz demand clock (sa bits) for the tlink input. see section 18 for details. signal name: tlink signal description: transmit link data signal type: input if enabled, this pin will be sampled on the falling edge of tclk for data insertion into any combination of the sa bit positions (sa4 to sa8). see section 14.1 for details. signal name: tsync signal description: transmit sync signal type: input / output a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. via tcr1.1, the ds21354/554 can be programmed to output either a fra me or multiframe pulse at this pin. this pin can also be configured as an input via tcr1.0. see section 19 for details. signal name: tssync signal description: transmit system sync signal type: input only used when the transmit side elastic store is enabled. a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. should be tied low in applications that do not use the transmit side elastic store. signal name: tsig signal description: transmit signaling input signal type: input when enabled, this input will sample signaling bits for insertion into outgoing pcm e1 data stream. sampled on the falling edge of tclk when the transmit side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit side elastic store is enabled.
ds21354 & DS21554 17 of 117 signal name: teso signal description: transmit elastic store data output signal type: output updated on the rising edge of tclk with data out of the transmit side elastic store whether the elastic store is enabled or not. this pin is normally tied to tdata. signal name: tdata signal description: transmit data signal type: input sampled on the falling edge of tclk with data to be clocked through the transmit side formatter. this pin is normally tied to teso. signal name: tposo signal description: transmit positive data output signal type: output updated on the rising edge of tclko with the bipolar data out of the transmit side formatter. can be programmed to source nrz data via the output data format (tcr2.2) c ontrol bit. this pin is normally tied to tposi. signal name: tnego signal description: transmit negative data output signal type: output updated on the rising edge of tclko with the bipolar data out of the transmit side formatter. this pin is normally tied to tnegi. signal name: tclko signal description: transmit clock output signal type: output buffered output of signal that is clocking data through the transmit side formatter. this pin is normally tied to tclki. signal name: tposi signal description: transmit positive data input signal type: input sampled on the falling edge of tclki for data to be transmitted out onto the t1 line. can be internally connected to tposo by tying the liuc pin hig h. tposi and tnegi can be tied together in nrz applications. signal name: tnegi signal description: transmit negative data input signal type: input sampled on the falling edge of tclki for data to be transmitted out onto the t1 line. can be internally connected to tnego by tying the liuc pin high. tposi and tnegi can be tied together in nrz applications. signal name: tclki signal description: transmit clock input signal type: input line interface transmit clock. can be internally connected to tclko by tying the liuc pin high.
ds21354 & DS21554 18 of 117 4.1.2 receive side pins signal name: rlink signal description: receive link data signal type: output updated with the full recovered e1 data stream on the rising edge of rclk. signal name: rlclk signal description: receive link clock signal type: output 4 khz to 20 khz clock (sa bits) for the rlink output. see section 15 for details. signal name: rclk signal description: receive clock signal type: output 2.048 mhz clock that is used to clock da ta through the receive side framer. signal name: rchclk signal description: receive channel clock signal type: output a 256 khz clock which pulses high during the lsb of each channel. synchronous with rclk when the receive side elastic store is disa bled. synchronous with rsysclk when the receive side elastic store is enabled. useful for parallel to se rial conversion of channel data. signal name: rchblk signal description: receive channel block signal type: output a user programmable output that can be forced hi gh or low during any of the 32 e1 channels. synchronous with rclk when the receive side elas tic store is disabled. synchronous with rsysclk when the receive side elastic store is enabled. useful for blocking clocks to a serial uart or lapd controller in applications where not all e1 channels are used such as fractional e1, 384 kbps service, 768 kbps, or isdn?pri. also useful for locating indivi dual channels in drop?and?i nsert applications, for external per?channel loopback, and for per?ch annel conditioning. see section 12 for details. signal name: rser signal description: receive serial data signal type: output received nrz serial data. updated on rising edges of rclk when the receive side elastic store is disabled. updated on the rising ed ges of rsysclk when the receive side elastic store is enabled. signal name: rsync signal description: receive sync signal type: input/output an extracted pulse, one rclk wide, is output at this pin which identifies either frame or cas/crc multiframe boundaries. if the receive si de elastic store is enabled, then this pin can be enabled to be an input at which a frame or multiframe boundary pulse synchronous with rsysclk is applied.
ds21354 & DS21554 19 of 117 signal name: rfsync signal description: receive frame sync signal type: output an extracted 8 khz pulse, one rclk wide, is out put at this pin which identifies frame boundaries. signal name: rmsync signal description: receive multiframe sync signal type: output if the receive side elastic store is enabled, an extr acted pulse, one rsysclk wide , is output at this pin which identifies multiframe boundaries. if the receive side elastic store is disabled, then this output will output multiframe boundaries associated with rclk. signal name: rdata signal description: receive data signal type: output updated on the rising edge of rclk with the data out of the receive side framer. signal name: rsysclk signal description: receive system clock signal type: input 1.544 mhz , 2.048 mhz , 4.096 mhz or 8.192 mhz clock. only used when the receive side elastic store function is enabled. should be tied low in applications that do not use th e receive side elastic store. see section 18 on page 115 for details on 4.096 mhz a nd 8.192 mhz operation using the interleave bus option. signal name: rsig signal description: receive signaling output signal type: output outputs signaling bits in a pcm format. updated on rising edges of rclk when the receive side elastic store is disabled. updated on the rising edges of rsys clk when the receive side elastic store is enabled. signal name: rlos/lotc signal description: receive loss of sync / loss of transmit clock signal type: output a dual function output that is controlled by the tcr2.0 control bit. this pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the tclk pin has not been toggled for 5 sec. signal name: rcl signal description: receive carrier loss signal type: output set high when the line interface detects a carrier loss. signal name: rsigf signal description: receive signaling freeze signal type: output set high when the signaling data is frozen via either automatic or manual intervention. used to alert downstream equipment of the condition.
ds21354 & DS21554 20 of 117 signal name: 8mclk signal description: 8 mhz clock signal type: output an 8.192mhz clock output that is referenced to the clock that is output at the rclk pin. signal name: rposo signal description: receive positive data input signal type: output updated on the rising edge of rclko with bipolar data out of the line interface. this pin is normally tied to rposi. signal name: rnego signal description: receive negative data input signal type: output updated on the rising edge of rclko with the bipolar da ta out of the line interface. this pin is normally tied to rposi. signal name: rclko signal description: receive clock output signal type: output buffered recovered clock from the t1 line. this pin is normally tied to rclki. signal name: rposi signal description: receive positive data input signal type: input sampled on the falling edge of rclki for data to be clocked through the receive side framer. rposi and rnegi can be tied together for a nrz interface. can be internally connected to rposo by tying the liuc pin high. signal name: rnegi signal description: receive negative data input signal type: input sampled on the falling edge of rclki for data to be clocked through the receive side framer. rposi and rnegi can be tied together for a nrz interface. can be internally connected to rnego by tying the liuc pin high. signal name: rclki signal description: receive clock input signal type: input clock used to clock data through the receive side framer. this pin is normally tied to rclko. can be internally connected to rclko by tying the liuc pin high. 4.1.3 parallel control port pins signal name: int* signal description: interrupt signal type: output flags host controller during conditions and change of conditions defined in the status registers 1 and 2 and the hdlc status register. active low, open drain output
ds21354 & DS21554 21 of 117 signal name: fms signal description: framer mode select signal type: input selects the ds2154 mode when high or the ds21354/ 554 mode when low. if high, the jtrst* is internally pulled low. if low, jtrst* has nor mal jtag functionality. this pin has a 10k pull up resistor. signal name: test signal description: 3?state control signal type: input set high to 3?state all output a nd i/o pins (including the paralle l control port). set low for normal operation. useful in board level testing. signal name: mux signal description: bus operation signal type: input set low to select non?multiplexed bus operation. set high to select multiplexed bus operation. signal name: ad0 to ad7 signal description: data bus [d0 to d7] or address/data bus signal type: input in non?multiplexed bus operation (mux = 0), serves as the data bus. in multiplexed bus operation (mux = 1), serves as a 8?bit multiplexed address / data bus. signal name: a0 to a6 signal description: address bus signal type: input in non?multiplexed bus operation (mux = 0), serves as the address bus. in multiplexed bus operation (mux = 1), these pins are not used and should be tied low. signal name: bts signal description: bus type select signal type: input strap high to select motorola bus timing; strap low to select intel bus timing. this pin controls the function of the rd*(ds*), ale(as), and wr*(r/w*) pins. if bts = 1, then these pins assume the function listed in parenthesis (). signal name: rd*(ds*) signal description: read input - data strobe signal type: input rd* and ds* are active low signals. ds active high when mux = 1. see bus timing diagrams. signal name: cs* signal description: chip select signal type: input must be low to read or write to the device. cs* is an active low signal.
ds21354 & DS21554 22 of 117 signal name: ale(as)/a7 signal description: address latch enable(address strobe) or a7 signal type: input in non?multiplexed bus operation (mux = 0), serves as the upper address bit. in multiplexed bus operation (mux = 1), serves to de-multiplex the bus on a positive?going edge. signal name: wr*(r/w*) signal description: write input(read/write) signal type: input wr* is an active low signal. 4.1.4 jtag test access port pins signal name: jtrst* signal description: ieee 1149.1 test reset signal type: input this signal is used to asynchronously reset the test access port controller. at power up, jtrst* must be toggled from low to high. this action will set the device into jtag device id mode enabling the test access port features. this pin has a 10k pull up resist or. when fms=1, this pin is tied low internally. tie jtrst* low if jtag is not used and the framer is in ds21354/554 mode (fms low). signal name: jtms signal description: ieee 1149.1 test mode select signal type: input this pin is sampled on the rising edge of jtclk and is used to place the test access port into the various defined ieee 1149.1 states. this pin has a 10k pull up resistor. signal name: jtclk signal description: ieee 1149.1 test clock signal signal type: input this signal is used to shift data into jtdi on the rising edge and out of jtdo on the falling edge. signal name: jtdi signal description: ieee 1149.1 test data input signal type: input test instructions and data are cloc ked into this pin on the rising edge of jtclk. this pin has a 10k pull up resistor. signal name: jtdo signal description: ieee 1149.1 test data output signal type: output test instructions and data are clocked out of this pin on the falling edge of jtclk. if not used, this pin should be left unconnected.
ds21354 & DS21554 23 of 117 4.1.5 interleave bus operation pins signal name: ci signal description: carry in signal type: input a rising edge on this pin causes rser and rsig to co me out of high z state and tser and tsig to start sampling on the next rising edge of rsysclk/tsysclk beginning an i/o sequence of 8 or 256 bits of data. this pin has a 10k pull up resistor. signal name: co signal description: carry out signal type: output an output that is set high when the last bit of the 8 or 256 ibo output sequence has occurred on rser and rsig. 4.1.6 line interface pins signal name: mclk signal description: master clock input signal type: input a 2.048 mhz (+/-50 ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data recovery and fo r jitter attenuation. a quartz crystal of 2.048 mhz may be applied across mclk and xtald inst ead of the ttl level clock source. signal name: xtald signal description: quartz crystal driver signal type: output a quartz crystal of 2.048 mhz may be applied across mclk and xtald instead of a ttl level clock source at mclk. leave open circuited if a ttl clock source is applied at mclk. signal name: 8xclk signal description: eight times clock signal type: output a 16.384 mhz clock that is frequency locked to the 2.048 mhz clock provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from the tclki pin (if the jitter attenuator is enabled on the transmit side). can be internally disabled via test2 register if not needed. signal name: liuc signal description: line interface connect signal type: input tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the tposi/tnegi/tclki/rposi/rnegi/rclki pins. tie high to connect the line interface circuitry to the framer/formatter circuitry and deactivate the tposi/tnegi/tclki/rposi/rnegi/rclki pins. when liuc is tied high, the tposi/tnegi/tclki/ rposi/rnegi/rclki pins should be tied low. signal name: rtip & rring signal description: receive tip and ring signal type: input analog inputs for clock recovery circ uitry. these pins connect via a 1: 1 transformer to the e1 line. see section 16 for details. signal name: ttip & tring
ds21354 & DS21554 24 of 117 signal description: transmit tip and ring signal type: output analog line driver outputs. these pi ns connect via a step?up transformer to the e1 line. see section 0 for details. 4.1.7 supply pins signal name: dvdd signal description: digital positive supply signal type: supply 5.0 volts +/-5% (DS21554) or 3.3 volts +/-5% (ds 21354). should be tied to the rvdd and tvdd pins. signal name: rvdd signal description: receive analog positive supply signal type: supply 5.0 volts +/-5% (DS21554) or 3.3 volts +/-5% (ds21354) . should be tied to the dvdd and tvdd pins. signal name: tvdd signal description: transmit analog positive supply signal type: supply 5.0 volts +/-5% (DS21554) or 3.3 volts +/-5% (ds 21354). should be tied to the rvdd and dvdd pins. signal name: dvss signal description: digital signal ground signal type: supply 0.0 volts. should be tied to the rvss and tvss pins. signal name: rvss signal description: receive analog signal ground signal type: supply 0.0 volts. should be tied to dvss and tvss. signal name: tvss signal description: transmit analog signal ground signal type: supply 0.0 volts. should be tied to dvss and rvss. 5 parallel port the ds21354/554 is controlled via either a non?multip lexed (mux = 0) or a multiplexed (mux = 1) bus by an external microcontroller or microprocessor. the device can operate with either intel or motorola bus timing configurations. if the bts pin is tied low, intel timing will be selected; if tied high, motorola timing will be selected. all motorola bus signals are listed in parenthesis (). see the timing diagrams in the a.c. electrical characteristics in section 21 for more details.
ds21354 & DS21554 25 of 117 5.1 register map register map sorted by address table 5-1 address r/w register name register abbreviation 00 r bpv or code violation count 1 vcr1 01 r bpv or code violation count 2 vcr2 02 r crc4 error count 1 / fas error count 1 crccr1 03 r crc4 error count 2 crccr2 04 r e-bit count 1 / fas error count 2 ebcr1 05 r e-bit count 2 ebcr2 06 r/w status 1 sr1 07 r/w status 2 sr2 08 r/w receive information rir 09 ? not used (set to 00h) 0a ? not used (set to 00h) 0b ? not used (set to 00h) 0c ? not used (set to 00h) 0d ? not used (set to 00h) 0e ? not used (set to 00h) 0f r device id idr 10 r/w receive control 1 rcr1 11 r/w receive control 2 rcr2 12 r/w transmit control 1 tcr1 13 r/w transmit control 2 tcr2 14 r/w common control 1 ccr1 15 r/w test 1 test1 (set to 00h) 16 r/w interrupt mask 1 imr1 17 r/w interrupt mask 2 imr2 18 r/w line interface control register licr 19 r/w test 2 test2 (set to 00h) 1a r/w common control 2 ccr2 1b r/w common control 3 ccr3 1c r/w transmit sa bit control tsacr 1d r/w common control 6 ccr6 1e r synchronizer status ssr 1f r receive non-align frame rnaf 20 r/w transmit align frame taf 21 r/w transmit non-align frame tnaf 22 r/w transmit channel blocking 1 tcbr1 23 r/w transmit channel blocking 2 tcbr2 24 r/w transmit channel blocking 3 tcbr3 25 r/w transmit channel blocking 4 tcbr4 26 r/w transmit idle 1 tir1 27 r/w transmit idle 2 tir2 28 r/w transmit idle 3 tir3 29 r/w transmit idle 4 tir4
ds21354 & DS21554 26 of 117 address r/w register name register abbreviation 2a r/w transmit idle definition tidr 2b r/w receive channel blocking 1 rcbr1 2c r/w receive channel blocking 2 rcbr2 2d r/w receive channel blocking 3 rcbr3 2e r/w receive channel blocking 4 rcbr4 2f r receive align frame raf 30 r receive signaling 1 rs1 31 r receive signaling 2 rs2 32 r receive signaling 3 rs3 33 r receive signaling 4 rs4 34 r receive signaling 5 rs5 35 r receive signaling 6 rs6 36 r receive signaling 7 rs7 37 r receive signaling 8 rs8 38 r receive signaling 9 rs9 39 r receive signaling 10 rs10 3a r receive signaling 11 rs11 3b r receive signaling 12 rs12 3c r receive signaling 13 rs13 3d r receive signaling 14 rs14 3e r receive signaling 15 rs15 3f r receive signaling 16 rs16 40 r/w transmit signaling 1 ts1 41 r/w transmit signaling 2 ts2 42 r/w transmit signaling 3 ts3 43 r/w transmit signaling 4 ts4 44 r/w transmit signaling 5 ts5 45 r/w transmit signaling 6 ts6 46 r/w transmit signaling 7 ts7 47 r/w transmit signaling 8 ts8 48 r/w transmit signaling 9 ts9 49 r/w transmit signaling 10 ts10 4a r/w transmit signaling 11 ts11 4b r/w transmit signaling 12 ts12 4c r/w transmit signaling 13 ts13 4d r/w transmit signaling 14 ts14 4e r/w transmit signaling 15 ts15 4f r/w transmit signaling 16 ts16 50 r/w transmit si bits align frame tsiaf 51 r/w transmit si bits non-align frame tsinaf 52 r/w transmit remote alarm bits tra 53 r/w transmit sa4 bits tsa4 54 r/w transmit sa5 bits tsa5 55 r/w transmit sa6 bits tsa6 56 r/w transmit sa7 bits tsa7
ds21354 & DS21554 27 of 117 address r/w register name register abbreviation 57 r/w transmit sa8 bits tsa8 58 r receive si bits align frame rsiaf 59 r receive si bits non-align frame rsinaf 5a r receive remote alarm bits rra 5b r receive sa4 bits rsa4 5c r receive sa5 bits rsa5 5d r receive sa6 bits rsa6 5e r receive sa7 bits rsa7 5f r receive sa8 bits rsa8 60 r/w transmit channel 1 tc1 61 r/w transmit channel 2 tc2 62 r/w transmit channel 3 tc3 63 r/w transmit channel 4 tc4 64 r/w transmit channel 5 tc5 65 r/w transmit channel 6 tc6 66 r/w transmit channel 7 tc7 67 r/w transmit channel 8 tc8 68 r/w transmit channel 9 tc9 69 r/w transmit channel 10 tc10 6a r/w transmit channel 11 tc11 6b r/w transmit channel 12 tc12 6c r/w transmit channel 13 tc13 6d r/w transmit channel 14 tc14 6e r/w transmit channel 15 tc15 6f r/w transmit channel 16 tc16 70 r/w transmit channel 17 tc17 71 r/w transmit channel 18 tc18 72 r/w transmit channel 19 tc19 73 r/w transmit channel 20 tc20 74 r/w transmit channel 21 tc21 75 r/w transmit channel 22 tc22 76 r/w transmit channel 23 tc23 77 r/w transmit channel 24 tc24 78 r/w transmit channel 25 tc25 79 r/w transmit channel 26 tc26 7a r/w transmit channel 27 tc27 7b r/w transmit channel 28 tc28 7c r/w transmit channel 29 tc29 7d r/w transmit channel 30 tc30 7e r/w transmit channel 31 tc31 7f r/w transmit channel 32 tc32 80 r/w receive channel 1 rc1 81 r/w receive channel 2 rc2 82 r/w receive channel 3 rc3 83 r/w receive channel 4 rc4
ds21354 & DS21554 28 of 117 address r/w register name register abbreviation 84 r/w receive channel 5 rc5 85 r/w receive channel 6 rc6 86 r/w receive channel 7 rc7 87 r/w receive channel 8 rc8 88 r/w receive channel 9 rc9 89 r/w receive channel 10 rc10 8a r/w receive channel 11 rc11 8b r/w receive channel 12 rc12 8c r/w receive channel 13 rc13 8d r/w receive channel 14 rc14 8e r/w receive channel 15 rc15 8f r/w receive channel 16 rc16 90 r/w receive channel 17 rc17 91 r/w receive channel 18 rc18 92 r/w receive channel 19 rc19 93 r/w receive channel 20 rc20 94 r/w receive channel 21 rc21 95 r/w receive channel 22 rc22 96 r/w receive channel 23 rc23 97 r/w receive channel 24 rc24 98 r/w receive channel 25 rc25 99 r/w receive channel 26 rc26 9a r/w receive channel 27 rc27 9b r/w receive channel 28 rc28 9c r/w receive channel 29 rc29 9d r/w receive channel 30 rc30 9e r/w receive channel 31 rc31 9f r/w receive channel 32 rc32 a0 r/w transmit channel control 1 tcc1 a1 r/w transmit channel control 2 tcc2 a2 r/w transmit channel control 3 tcc3 a3 r/w transmit channel control 4 tcc4 a4 r/w receive channel control 1 rcc1 a5 r/w receive channel control 2 rcc2 a6 r/w receive channel control 3 rcc3 a7 r/w receive channel control 4 rcc4 a8 r/w common control 4 ccr4 a9 r transmit ds0 monitor tds0m aa r/w common control 5 ccr5 ab r receive ds0 monitor rds0m ac r/w test 3 test3 (set to 00h) ad - not used (set to 00h) ae - not used (set to 00h) af - not used (set to 00h) b0 r/w hdlc control register hcr
ds21354 & DS21554 29 of 117 address r/w register name register abbreviation b1 r/w hdlc status register hsr b2 r/w hdlc interrupt mask register himr b3 r/w receive hdlc information register rhir b4 r/w receive hdlc fifo register rhfr b5 r/w interleave bus operation register ibo b6 r/w transmit hdlc information register thir b7 r/w transmit hdlc fifo register thfr b8 r/w receive hdlc ds0 control register 1 rdc1 b9 r/w receive hdlc ds0 control register 2 rdc2 ba r/w transmit hdlc ds0 control register 1 tdc1 bb r/w transmit hdlc ds0 control register 2 tdc2 bc - not used (set to 00h) bd - not used (set to 00h) be - not used (set to 00h) bf - not used (set to 00h) notes: 1. test registers are used only by the factory; these registers must be cleared (set to all zeros) on power? up initialization to insure proper operation. 2. register banks cxh, dxh, exh, and fxh are not accessible. 6 control, id, and test registers the operation of the ds21354/554 is configured via a set of ten control registers. typically, the control registers are only accessed when the system is firs t powered up. once the device has been initialized, the control registers will only need to be accessed when th ere is a change in the system configuration. there are two receive control register (rcr1 and rcr2), two transmit control registers (tcr1 and tcr2), and six common control registers (ccr1 to ccr6). each of the ten registers are described in this section. there is a device identification re gister (idr) at address 0fh. the msb of this read?only register is fixed to a one indicating that an e1 sct is present. the next 3 msbs are used to indicate which e1 device is present; ds2154, ds21354, or DS21554. the t1 pin?for?pin compatible scts will have a logic zero in the msb position with the following 3 msbs indicating which t1 sct is present; ds2152, ds21352, or ds21552. table 4-1 represents the possible variations of thes e bits and the associated sct. device id bit map table 6-1 sct t1/e1 bit 6 bit 5 bit 4 ds2152 0 0 0 0 ds21352 0 0 0 1 ds21552 0 0 1 0 ds2154 1 0 0 0 ds21354 1 0 0 1 DS21554 1 0 1 0 the lower four bits of the idr are used to display the die revision of the chip.
ds21354 & DS21554 30 of 117 the test registers at addresses 09, 15, 19, and ac hex are used by the factory in testing the ds21354/554. on power-up, the test registers shoul d be set to 00h in order for the ds21354/554 to operate properly. 6.1 power?up sequence on power?up, after the supplies are stable the ds21354/554 should be configured for operation by writing to all of the internal registers (this includes setting the test registers to 00h) since the contents of the internal registers cannot be predicted on po wer?up. the lirst (ccr5.7) should be toggled from zero to one to reset the line interface circuitry (it will take the devi ce about 40ms to recover from the lirst bit being toggled). finally, after the ts ysclk and rsysclk inputs are stable, the esr bits (ccr6.0 & ccr6.1) should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled). idr: device identi fication register (address=0f hex) (msb) ( lsb) t1e1 bit 6 bit 5 bit 4 id3 id2 id1 id0 symbol position name and description t1e1 idr.7 t1 or e1 chip determination bit. set to 1. 0=t1 chip 1=e1 chip bit 6 idr.6 bit 6. see table 6-1 bit 5 idr.5 bit 5. see table 6-1 bit 4 idr.4 bit 4. see table 6-1 id3 idr.3 chip revision bit 3. msb of a decimal code that represents the chip revision. id2 idr.1 chip revision bit 2. id1 idr.2 chip revision bit 1. id0 idr.0 chip revision bit 0. lsb of a decimal code that represents the chip revision. rcr1: receive control register 1 (address=10 hex) (msb) (lsb) rsmf rsm rsio ? ? frc synce resync symbol position name and description rsmf rcr1.7 rsync multiframe function. only used if the rsync pin is programmed in the multi frame mode (rcr1.6=1). 0 = rsync outputs cas multiframe boundaries 1 = rsync outputs crc4 multiframe boundaries rsm rcr1.6 rsync mode select. 0 = frame mode (see the timing in section 19-1) 1 = multiframe mode (see the timing in section 19-1) rsio rcr1.5 rsync i/o select. (note: this b it must be set to zero when rcr2.1=0). 0 = rsync is an output (depends on rcr1.6) 1 = rsync is an input (only va lid if elastic store enabled) ? rcr1.4 not assigned. should be set to zero when written.
ds21354 & DS21554 31 of 117 symbol position name and description ? rcr1.3 not assigned. should be set to zero when written. frc rcr1.2 frame resync criteria. 0 = resync if fas received in error 3 consecutive times 1 = resync if fas or bit 2 of non?fas is received in error 3 consecutive times synce rcr1.1 sync enable. 0 = auto resync enabled 1 = auto resync disabled resync rcr1.0 resync. when toggled from low to high, a resync is initiated. must be cleared and set again for a subsequent resync. 6.1.1 synchronization and re-synchronization once synchronization is accomplished there are certain criteria that can cause a re-synchronization. these criteria are detailed in table 6-2. also see figure 19-14 for a flow chart of the synchronization process. sync/resync criteria table 6-2 frame or multiframe level sync criteria resync criteria itu spec. fas fas present in frame n and n + 2, and fas not present in frame n + 1 three consecutive incorrect fas received alternate (rcr1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non?fas received g.706 4.1.1 4.1.2 crc4 two valid mf alignment words found within 8 ms 915 or more crc4 code words out of 1000 received in error g.706 4.2 and 4.3.2 cas valid mf alignment word found and previous timeslot 16 contains code other than all zeros two consecutive mf alignment words received in error g.732 5.2
ds21354 & DS21554 32 of 117 rcr2: receive control register 2 (address=11 hex) (msb) (lsb) sa8s sa7s sa6s sa5s sa4s rbcs rese ? symbol position name and description sa8s rcr2.7 sa8 bit select. set to one to have rlclk pulse at the sa8 bit position; set to zero to force rlclk low during sa8 bit position. see section 19.1 for timing details. sa7s rcr2.6 sa7 bit select. set to one to have rlclk pulse at the sa7 bit position; set to zero to force rlclk low during sa7 bit position. see section 19.1 for timing details. sa6s rcr2.5 sa6 bit select. set to one to have rlclk pulse at the sa6 bit position; set to zero to force rlclk low during sa6 bit position. see section 19.1 for timing details. sa5s rcr2.4 sa5 bit select. set to one to have rlclk pulse at the sa5 bit position; set to zero to force rlclk low during sa5 bit position. see section 19.1 for timing details. sa4s rcr2.3 sa4 bit select. set to one to have rlclk pulse at the sa4 bit position; set to zero to force rlclk low during sa4 bit position. see section 19.1 for timing details. rbcs rcr2.2 receive side backplane clock select. 0 = if rsysclk is 1.544 mhz 1 = if rsysclk is 2.048/4.096/8.192 mhz rese rcr2.1 receive side elastic store enable. 0 = elastic store is bypassed 1 = elastic store is enabled ? rcr2.0 not assigned. should be set to zero when written. tcr1: transmit control register 1 (address=12 hex) (msb) (lsb) odf tfpt t16s tua1 tsis tsa1 tsm tsio symbol position name and description odf tcr1.7 output data format. 0 = bipolar data at tposo and tnego 1 = nrz data at tposo; tnego=0 tfpt tcr1.6 transmit timeslot 0 pass through. 0 = fas bits/sa bits/remote alarm sourced internally from the taf and tnaf registers 1 = fas bits/sa bits/remot e alarm sourced from tser t16s tcr1.5 transmit timeslot 16 data select. 0 = sample timeslot 16 at tser pin 1 = source timeslot 16 from ts0 to ts15 registers tua1 tcr1.4 transmit unframed all ones. 0 = transmit data normally 1 = transmit an unframed all one?s code at tposo and tnego
ds21354 & DS21554 33 of 117 symbol position name and description tsis tcr1.3 transmit international bit select. 0 = sample si bits at tser pin 1 = source si bits from taf and tnaf registers (in this mode, tcr1.6 must be set to 0) tsa1 tcr1.2 transmit signaling all ones. 0 = normal operation 1 = force timeslot 16 in every frame to all ones tsm tcr1.1 tsync mode select. 0 = frame mode (see the timing in section 19.2) 1 = cas and crc4 multiframe mode (see the timing in section 19.2) tsio tcr1.0 tsync i/o select. 0 = tsync is an input 1 = tsync is an output note: see figure 19-15 for more details about how the tran smit control registers affe ct the operation of the ds21354/554. tcr2: transmit control register 2 (address=13 hex) (msb) (lsb) sa8s sa7s sa6s sa5s sa4s odm aebe pf symbol position name and description sa8s tcr2.7 sa8 bit select. set to one to source the sa8 bit from the tlink pin; set to zero to not source the sa8 bit. see section 19.2 for timing details. sa7s tcr2.6 sa7 bit select. set to one to source the sa7 bit from the tlink pin; set to zero to not source the sa7 bit. see section 19.2 for timing details. sa6s tcr2.5 sa6 bit select. set to one to source the sa6 bit from the tlink pin; set to zero to not source the sa6 bit. see section 19.2 for timing details. sa5s tcr2.4 sa5 bit select. set to one to source the sa5 bit from the tlink pin; set to zero to not source the sa5 bit. see section 19.2 for timing details. sa4s tcr2.3 sa4 bit select. set to one to source the sa4 bit from the tlink pin; set to zero to not source the sa4 bit. see section 19.2 for timing details. odm tcr2.2 output data mode. 0 = pulses at tposo and tnego are one full tclko period wide 1 = pulses at tposo and tneg o are 1/2 tclko period wide aebe tcr2.1 automatic e?bit enable. 0 = e?bits not automatically set in the transmit direction 1 = e?bits automatically set in the transmit direction pf tcr2.0 function of rlos/lotc pin. 0 = receive loss of sync (rlos) 1 = loss of transmit clock (lotc)
ds21354 & DS21554 34 of 117 ccr1: common control register 1 (address=14 hex) (msb) (lsb) flb thdb3 tg802 tcrc4 rsm rhdb3 rg802 rcrc4 symbol position name and description flb ccr1.7 framer loopback. 0 = loopback disabled 1 = loopback enabled thdb3 ccr1.6 transmit hdb3 enable. 0 = hdb3 disabled 1 = hdb3 enabled tg802 ccr1.5 transmit g.802 enable. see section 19 for details. 0 = do not force tchblk high during bit 1 of timeslot 26 1 = force tchblk high during bit 1 of timeslot 26 tcrc4 ccr1.4 transmit crc4 enable. 0 = crc4 disabled 1 = crc4 enabled rsm ccr1.3 receive signaling mode select. 0 = cas signaling mode 1 = ccs signaling mode rhdb3 ccr1.2 receive hdb3 enable. 0 = hdb3 disabled 1 = hdb3 enabled rg802 ccr1.1 receive g.802 enable. see section 19 for details. 0 = do not force rchblk high during bit 1 of timeslot 26 1=force rchblk high during bit 1 of timeslot 26 rcrc4 ccr1.0 receive crc4 enable. 0 = crc4 disabled 1 = crc4 enabled 6.2 framer loopback when ccr1.7 is set to a one, the ds21354/554 will en ter a framer loopback (flb) mode. see figure 3-1 for more details. this loopback is useful in tes ting and debugging applicati ons. in flb, the sct will loop data from the transmit side back to the receive side. when flb is enabled, the following will occur: 1. data will be transmitted as normal at tposo and tnego. 2. data input via rposi a nd rnegi will be ignored. 3. the rclk output will be replaced with the tclk input.
ds21354 & DS21554 35 of 117 ccr2: common control register 2 (address=1a hex) (msb) (lsb) ecus vcrfs aais ara rserc lotcmc rff rfe symbol position name and description ecus ccr2.7 error counter update select. see section 8 for details. 0 = update error counters once a second 1 = update error counters every 62.5 ms (500 frames) vcrfs ccr2.6 vcr function select. see section 8.1 for details. 0 = count bipolar violations (bpvs) 1 = count code violations (cvs) aais ccr2.5 automatic transmit ais generation. 0 = disabled 1 = enabled ara ccr2.4 automatic remote alarm generation. 0 = disabled 1 = enabled rserc ccr2.3 rser control. 0 = allow rser to output data as received under all conditions 1 = force rser to one under lo ss of frame alignment conditions lotcmc ccr2.2 loss of transmit clock mux control. determines whether the transmit side formatter should switch to the ever present rclko if the tclk should fail to transition (see figure 3-1). 0 = do not switch to rclko if tclk stops 1 = switch to rclko if tclk stops rff ccr2.1 receive force freeze. freezes receive side signaling at rsig (and ts16 in rser if ccr3.3=1); will override receive freeze enable (rfe). see section 10.2 for details. 0 = do not force a freeze event 1 = force a freeze event rfe ccr2.0 receive freeze enable. see section 10.2 for details. 0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signa ling data at rsig (and ts16 in rser if ccr3.3 = 1). 6.3 automatic alarm generation the device can be programmed to automatically transmit ais or remote alarm. when automatic ais generation is enabled (ccr2.5 = 1), the device monitors th e receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, ais alarm (all one?s) reception, or loss of receive carrier (or signal). if any one (or more) of the above conditions is present, then the framer will either force an ais alarm. when automatic rai generation is enabled (ccr2.4 = 1), the framer monitors the receive side to determine if any of the following conditions are pr esent: loss of receive frame synchronization, ais alarm (all one?s) reception, or loss of receive carrier (or signal) or if crc4 multiframe synchronization cannot be found within 128ms of fas synchronization (if crc4 is enabled). if any one (or more) of the above conditions is present, then the framer will either transmit a rai alarm.
ds21354 & DS21554 36 of 117 rai generation conforms to ets 300 011 specifications and a constant remote alarm will be transmitted if the ds21354/554 cannot find crc4 multiframe synchronization within 400 ms as per g.706. ccr3: common control register 3 (address=1b hex) (msb) (lsb) tese tcbfs tirfs ? rsre thse tbcs rcla symbol position name and description tese ccr3.7 transmit side elastic store enable. 0 = elastic store is bypassed 1 = elastic store is enabled tcbfs ccr3.6 transmit channel bloc king registers (tcbr) function select. 0 = tcbrs define the operati on of the tchblk output pin 1 = tcbrs define which signaling bits are to be inserted tirfs ccr3.5 transmit idle registers (tir) function select. see section 11.1 for details. 0 = tirs define in which ch annels to insert idle code 1 = tirs define in which channels to insert data from rser (i.e., per=channel loopback function) - ccr3.4 not assigned. should be set to zero when written to. rsre ccr3.3 receive side signaling re?insertion enable. see section 10.2.1 for details. 0 = do not re?insert signaling bits into the data stream presented at the rser pin 1 = re?insert the signaling bits into da ta stream presented at the rser pin thse ccr3.2 transmit side hardware si gnaling insertion enable. see section 10.2.2 for details. 0 = do not insert signaling from the tsig pin into the data stream presented at the tser pin 1 = insert signaling from the tsig pin into the data stream presented at the tser pin tbcs ccr3.1 transmit side backplane clock select. 0 = if tsysclk is 1.544 mhz 1 = if tsysclk is 2.048/4.096/8.192 mhz rcla ccr3.0 receive carrier loss (rcl) alternate criteria. 0 = rcl declared upon 255 consecutive zeros (125 us) 1 = rcl declared upon 2048 consecutive zeros (1 ms) ccr4: common control register 4 (address=a8 hex) (msb) (lsb) rlb llb liais tcm4 tcm3 tcm2 tcm1 tcm0 symbol position name and description rlb ccr4.7 remote loopback. 0 = loopback disabled 1 = loopback enabled
ds21354 & DS21554 37 of 117 symbol position name and description llb ccr4.6 local loopback. 0 = loopback disabled 1 = loopback enabled liais ccr4.5 line interface ais generation enable. 0 = allow normal data from tposi/tnegi to be transmitted at ttip and tring 1 = force unframed all ones to be transmitted at ttip and tring at the mclk rate tcm4 ccr4.4 transmit channel monitor bit 4. msb of a channel decode that determines which transmit channel data will appear in the tds0m register. see section 9 for details. tcm3 ccr4.3 transmit channel monitor bit 3. tcm2 ccr4.2 transmit channel monitor bit 2. tcm1 ccr4.1 transmit channel monitor bit 1. tcm0 ccr4.0 transmit channel monitor bit 0. lsb of the channel decode. 6.4 remote loopback when ccr4.7 is set to a one, the sct will be forced into remote l oopback (rlb). in this loopback, data input via the rposi and rnegi pins will be transmitted back to the tposo and tnego pins. data will continue to pass through the receive side framer of the sct as it would normally and the data from the transmit side formatter will be ignored. please see figure 3-1 for more details. 6.5 local loopback when ccr4.6 is set to a one, the sct will be forced into local loopback (llb). in this loopback, data will continue to be transmitted as normal through the transmit side of the sct. data being received at rtip and rring will be replaced with the data being transmitted. data in this loopback will pass through the jitter attenuator. please see figure 3-1 for more details. ccr5: common control register 5 (address=aa hex) (msb) (lsb) lirst resa tesa rcm4 rcm3 rcm2 rcm1 rcm0 symbol position name and description lirst ccr5.7 line interface reset. setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. normally this bit is only toggled on power?up. must be cleared and set again for a subsequent reset. resa ccr5.6 receive elastic store align. setting this bit from a zero to a one may force the receive elastic store?s write/read pointers to a minim separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a fra me. if pointer separation is less then half a frame, the command will be executed and data will be disrupted.
ds21354 & DS21554 38 of 117 symbol position name and description should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subs equent align. see section 13 for details. tesa ccr5.5 transmit elastic store align. setting this bit from a zero to a one may force the transmit elastic store?s write/read pointers to a minim separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a fra me. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after tsysclk has been applied and is stable. must be cleared and set again for a subs equent align. see section 13 for details. rcm4 ccr5.4 receive channel monitor bit 4 . msb of a channel decode that determines which receive channel data will appear in the rds0m register. see section 9 for details. rcm3 ccr5.3 receive channel monitor bit 3. rcm2 ccr5.2 receive channel monitor bit 2. rcm1 ccr5.1 receive channel monitor bit 1. rcm0 ccr5.0 receive channel monitor bit 0. lsb of the channel decode. ccr6: common control register 6 (address=1d hex) (msb) (lsb) liuodo cdig liusi ? ? tclksrc resr tesr symbol position name and description liuodo ccr6.7 line interface open drain option. this control bit determines whether the ttip and tring outputs will be open drain or not. the line driver outputs can be forced open drain to a llow 6vpeak pulses to be generated or to allow the creation of a very low power interface. 0 = allow ttip and tring to operate normally 1 = force the ttip and tring outputs to be open drain cdig ccr6.6 customer disconnect indication generator. this control bit determines whether the line interface will generate an unframed ...1010... pattern at ttip and tring inst ead of the normal data pattern. 0 = generate normal data at ttip & tring as input via tposi & tnegi 1 = generate a ...1010... pattern at ttip and tring liusi ccr6.5 line interface g.703 synchron ization interface enable. this control bit determines whether the line recei ver should handle a normal e1 signal (section 6 of g.703) or a 2.048mhz synchronization signal (section 10 of g.703). this control has no aff ect on the line interface transmitter. 0 = line receiver configured to support a normal e1 signal 1 = line receiver configured to support a synchronization signal ? ccr6.4 not assigned. should be set to zero when written.
ds21354 & DS21554 39 of 117 symbol position name and description ? ccr6.3 not assigned. should be set to zero when written. tclksrc ccr6.2 transmit clock source select. this function allows the user to internally select rclk as the clock source for the transmit side formatter. 0 = source of transmit clock determined by ccr2.2 (lotcmc) 1 = force transmitter to internally switch to rclk as source of transmit clock. signal at tclk pin is ignored resr ccr6.1 receive elastic store reset. setting this bit from a zero to a one will force the receive elastic store to a depth of one frame. receive data is lost during the reset. should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subsequent reset. tesr ccr6.0 transmit elastic store reset. setting this bit from a zero to a one will force the transmit elastic store to a depth of one frame. transmit data is lost during the reset. should be togg led after tsysclk has been applied and is stable. must be cleared a nd set again for a subsequent reset. 7 status and information registers there is a set of seven registers that contain information on the current real time status of a framer in the ds21354/554, status register 1 (sr1), status register 2 (sr2), recei ve information register (rir), synchronizer status register (ssr ) and a set of three registers for the onboard hdlc controller. the specific details on the four register s pertaining to the hdlc controlle r are covered in section 15 but they operate the same as the other status registers in the device and this opera tion is described below. when a particular event has occurred (or is occurring) , the appropriate bit in one of these four registers will be set to a one. all of the b its in sr1, sr2, and rir1 registers operate in a latched fashion. the synchronizer status register contents are not latched. this means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the rua1, rra, rcl, and rlos alarms, the bit will remain set if the alarm is still present). the user will always proceed a read of any of the sr1, sr2 and rir registers with a write. the byte written to the register will inform the framer which bits the user wishes to read and have cleared. the user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. when a one is written to a bit location, the read register will be updated with the latest information. when a zero is written to a bit position, the read register will not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte th at was just written and th is value should be written back into the same register to insure that bit doe s indeed clear. this second write step is necessary because the alarms and events in th e status registers occur asynchronous ly in respect to their access via the parallel port. this write?read? write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. this operation is key in controlling the ds21354/554 with higher?order software languages. the ssr register operates differently than the other three. it is a read only register and it reports the status of the synchronizer in real time. this register is not latched and it is not necessary to precede a read of this register with a write.
ds21354 & DS21554 40 of 117 the sr1, sr2, and hsr registers have the unique ability to initiate a hardware interrupt via the int* output pin. each of the alarms and events in the sr1, sr2, and hsr can be e ither masked or unmasked from the interrupt pin via the interrupt mask register 1 (imr1), interrupt mask register 2 (imr2), and hdlc interrupt mask register (himr) respectivel y. the himr register is covered in section 15. the interrupts caused by alarms in sr1 (namely r ua1, rra, rcl, and rlos) act differently than the interrupts caused by events in sr1 and sr2 (nam ely rsa1, rdma, rsa0, rslip, rmf, tmf, sec, taf, lotc, rcmf, and tslip). the alarm caused interrupts will force the int* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in table 7-1). the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. the event caused interrupts will force the int* pin low when the event occurs. the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. rir: receive information register (address=08 hex) (msb) (lsb) tesf tese jalt resf rese crcrc fasrc casrc symbol position name and description tesf rir.7 transmit side elastic store full. set when the transmit side elastic store buffer fills and a frame is deleted. tese rir.6 transmit side elastic store empty. set when the transmit side elastic store buffer empties and a frame is repeated. jalt rir.5 jitter attenuator limit trip. set when the jitter attenuator fifo reaches to within 4?bits of its limit; useful for debugging jitter attenuation operation. resf rir.4 receive side elastic store full. set when the receive side elastic store buffer fills and a frame is deleted. rese rir.3 receive side elastic store empty. set when the receive side elastic store buffer empties and a frame is repeated. crcrc rir.2 crc resync criteria met. set when 915/1000 code words are received in error. fasrc rir.1 fas resync criteria met. set when 3 consecutive fas words are received in error. casrc rir.0 cas resync criteria met. set when 2 consecutive cas mf alignment words are received in error.
ds21354 & DS21554 41 of 117 ssr: synchronizer status register (address=1e hex) (msb) (lsb) csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa symbol position name and description csc5 ssr.7 crc4 sync counter bit 5. msb of the 6?bit counter. csc4 ssr.6 crc4 sync counter bit 4. csc3 ssr.5 crc4 sync counter bit 3. csc2 ssr.4 crc4 sync counter bit 2. csc0 ssr.3 crc4 sync counter bit 0. lsb of the 6?bit counter. the next to lsb is not accessible. fassa ssr.2 fas sync active. set while the synchronizer is searching for alignment at the fas level. cassa ssr.1 cas mf sync active. set while the synchronizer is searching for the cas mf alignment word. crc4sa ssr.0 crc4 mf sync active. set while the synchronizer is searching for the crc4 mf alignment word. 7.1 crc4 sync counter the crc4 sync counter increments each time the 8 ms crc4 multiframe search times out. the counter is cleared when the framer has successfully obtained synchronization at the crc4 level. the counter can also be cleared by disabling the crc4 mode (ccr1.0=0). this counter is useful for determining the amount of time the framer has been searching for synchronization at the crc4 level. itu g.706 suggests that if synchronization at the crc4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. the crc4 sync counter will rollover. sr1: status register 1 (address=06 hex) (msb) (lsb) rsa1 rdma rsa0 rslip rua1 rra rcl rlos symbol position name and description rsa1 sr1.7 receive signaling all ones / signaling change. set when the contents of timeslot 16 contains less than three zeros over 16 consecutive frames. this alarm is not disabled in the ccs signaling mode. both rsa1 and rsa0 will be set if a change in signaling is detected. rdma sr1.6 receive distant mf alarm. set when bit?6 of timeslot 16 in frame 0 has been set for two consecutive multi frames. this alarm is not disabled in the ccs signaling mode. rsa0 sr1.5 receive signaling all zeros / signaling change. set when over a full mf, timeslot 16 contains all zeros. both rsa1 and rsa0 will be set if a change in signaling is detected. rslip sr1.4 receive side elastic store slip. set when the elastic store has either repeated or deleted a frame of data. rua1 sr1.3 receive unframed all ones. set when an unframed all ones code is received at rposi and rnegi. rra sr1.2 receive remote alarm. set when a remote alarm is received at rposi and rnegi.
ds21354 & DS21554 42 of 117 symbol position name and description rcl sr1.1 receive carrier loss. set when 255 (or 2048 if ccr3.0=1) consecutive zeros have been detected at rtip and rring. (note: a receiver carrier loss based on data received at rposi and rnegi is available in the hsr register) rlos sr1.0 receive loss of sync. set when the device is not synchronized to the receive e1 stream. alarm criteria table 7-1 alarm set criteria clear criteria itu spec. rsa1 (receive signaling all ones) over 16 consecutive frames (one full mf) timeslot 16 contains less than three zeros over 16 consecutive frames (one full mf) timeslot 16 contains three or more zeros g.732 4.2 rsa0 (receive signaling all zeros) over 16 consecutive frames (one full mf) timeslot 16 contains all zeros over 16 consecutive frames (one full mf) timeslot 16 contains at least a single one g.732 5.2 rdma (receive distant multiframe alarm) bit 6 in timeslot 16 of frame 0 set to one for two consecutive mf bit 6 in timeslot 16 of frame 0 set to zero for two consecutive mf o.162 2.1.5 rua1 (receive unframed all ones) less than three zeros in two frames (512?bits) more than two zeros in two frames (512?bits) o.162 1.6.1.2 rra (receive remote alarm) bit 3 of non?align frame set to one for three consecutive occasions bit 3 of non?align frame set to zero for three consecutive occasions o.162 2.1.4 rcl (receive carrier loss) 255 (or 2048) consecutive zeros received in 255?bit times, at least 32 ones are received g.775 / g.962 sr2: status register 2 (address=07 hex) (msb) (lsb) rmf raf tmf sec taf lotc rcmf tslip symbol position name and description rmf sr2.7 receive cas multiframe. set every 2 ms (regardless if cas signaling is enabled or not) on receive multiframe boundaries. used to alert the host that signaling data is available. raf sr2.6 receive align frame. set every 250 ns at the beginning of align frames. used to alert the host that si and sa bits are available in the raf and rnaf registers. tmf sr2.5 transmit multiframe. set every 2 ms (regardless if crc4 is enabled) on transmit multiframe boundaries. used to alert the host that signaling data needs to be updated. sec sr2.4 one second timer. set on increments of one second based on rclk. if ccr2.7=1, then this bit will be set every 62.5 ms instead of once a second.
ds21354 & DS21554 43 of 117 symbol position name and description taf sr2.3 transmit align frame. set every 250 ns at the beginning of align frames. used to alert the host that the taf and tnaf registers need to be updated. lotc sr2.2 loss of transmit clock. set when the tclk pin has not transitioned for one channel time (or 3.9 ns). will force the lotc pin high if enabled via tcr2.0. rcmf sr2.1 receive crc4 multiframe. set on crc4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if crc4 is disabled. tslip sr2.0 transmit elastic store slip. set when the elastic store has either repeated or deleted a frame of data. imr1: interrupt mask register 1 (address=16 hex) (msb) (lsb) rsa1 rdma rsa0 rslip rua1 rra rcl rlos symbol position name and description rsa1 imr1.7 receive signaling all ones / signaling change. 0 = interrupt masked 1 = interrupt enabled rdma imr1.6 receive distant mf alarm. 0 = interrupt masked 1 = interrupt enabled rsa0 imr1.5 receive signaling all zeros / signaling change. 0 = interrupt masked 1 = interrupt enabled rslip imr1.4 receive elastic store slip occurrence. 0 = interrupt masked 1 = interrupt enabled rua1 imr1.3 receive unframed all ones. 0 = interrupt masked 1 = interrupt enabled rra imr1.2 receive remote alarm. 0 = interrupt masked 1 = interrupt enabled rcl imr1.1 receive carrier loss. 0 = interrupt masked 1 = interrupt enabled rlos imr1.0 receive loss of sync. 0 = interrupt masked 1 = interrupt enabled
ds21354 & DS21554 44 of 117 imr2: interrupt mask register 2 (address=17 hex) (msb) (lsb) rmf raf tmf sec taf lotc rcmf tslip symbol position name and description rmf imr2.7 receive cas multiframe. 0 = interrupt masked 1 = interrupt enabled raf imr2.6 receive align frame. 0 = interrupt masked 1 = interrupt enabled tmf imr2.5 transmit multiframe. 0 = interrupt masked 1 = interrupt enabled sec imr2.4 one second timer. 0 = interrupt masked 1 = interrupt enabled taf imr2.3 transmit align frame. 0 = interrupt masked 1 = interrupt enabled lotc imr2.2 loss of transmit clock. 0 = interrupt masked 1 = interrupt enabled rcmf imr2.1 receive crc4 multiframe. 0 = interrupt masked 1 = interrupt enabled tslip imr2.0 transmit side elastic store slip occurrence. 0 = interrupt masked 1 = interrupt enabled 8 error count registers there are a set of four counters in the ds21354/554 that record bipolar or code violations, errors in the crc4 smf code words, e bits as reported by the far end, and word errors in the fas. each of these four counters are automatically updated on either one second boundaries (ccr2.7 = 0) or every 62.5 ms (ccr2.7 = 1) as determined by the timer in status register 2 (sr2.4). hence, these registers contain performance data from either the previous second or the previous 62.5 ms. the user can use the interrupt from the one second timer to determin e when to read these registers. the user has a full second (or 62.5 ms) to read the counters before the data is lost. all four counters will satu rate at their respective maximum counts and they will not rollover. 8.1 bpv or code violation counter violation count register 1 (vcr1) is the most signific ant word and vcr2 is the least significant word of a 16?bit counter that records either bipolar violations (bpvs) or code violations (cvs). if ccr2.6 = 0, then the vcr counts bipolar violati ons. bipolar violations are defined as consecutive marks of the same polarity. in this mode, if the hdb3 mode is set fo r the receive side via ccr1.2, then hdb3 code words are not counted as bpvs. if ccr2.6 = 1, then the vcr counts code violations as defined in itu o.161. code violations are defined as consecutive bipolar violations of the same polarity.
ds21354 & DS21554 45 of 117 in most applications, the framer should be programme d to count bpvs when receiving ami code and to count cvs when receiving hdb3 code. this counter incr ements at all times and is not disabled by loss of sync conditions. the counter satura tes at 65,535 and will not rollover. the bit error rate on an e1 line would have to be greater than 10**?2 before the vcr would saturate. vcr1: upper bipolar viol ation count register 1 (address=00 hex) vcr2: lower bipolar violation count register 2 (address=01 hex) (msb) (lsb) v15 v14 v13 v12 v11 v10 v9 v8 vcr1 v7 v6 v5 v4 v3 v2 v1 v0 vcr2 symbol position name and description v15 vcr1.7 msb of the 16?bit code violation count v0 vcr2.0 lsb of the 16?bit code violation count 8.2 crc4 error counter crc4 count register 1 (crccr1) is the most signif icant word and crccr2 is the least significant word of a 10?bit counter that records word errors in the cyclic redundancy check 4 (crc4). since the maximum crc4 count in a one second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it will continue to count if loss of multiframe sync occurs at the cas level. crccr1: crc4 count register 1 (address=02 hex) crccr2: crc4 count register 2 (address=03 hex) (msb) (lsb) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) crc9 crc8 crccr1 crc7 crc6 crc5 crc4 crc/3 crc2 crc1 crc0 crccr2 symbol position name and description crc9 crccr1.1 msb of the 10?bit crc4 error count crc0 crccr2.0 lsb of the 10?bit crc4 error count note: the upper six bits of crccr1 at address 02 are the mo st significant bits of the 12?bit fas error counter. 8.3 e?bit counter e?bit count register 1 (ebcr1) is the most signifi cant word and ebcr2 is the least significant word of a 10?bit counter that records far end block errors (febe) as reported in the first bit of frames 13 and 15 on e1 lines running with crc4 multiframe. these count registers will increment once each time the received e?bit is set to zero. since the maximum e ?bit count in a one second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it will continue to count if loss of multifra me sync occurs at the cas level.
ds21354 & DS21554 46 of 117 ebcr1: e?bit count register 1 (address=04 hex) ebcr2: e?bit count register 2 (address=05 hex) (msb) (lsb) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) eb9 eb8 ebcr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ebcr2 symbol position name and description eb9 ebcr1.1 msb of the 10?bit e?bit error count eb0 ebcr2.0 lsb of the 10?bit e?bit error count note: the upper six bits of ebcr1 at address 04 are the le ast significant bits of the 12?bit fas error counter. 8.4 fas error counter fas count register 1 (fascr1) is the most signifi cant word and fascr2 is the least significant word of a 12?bit counter that records word errors in the frame alignment signal in timeslot 0. this counter is disabled when rlos is high. fas errors will not be counted when the fram er is searching for fas alignment and/or synchronization at either the cas or crc4 multiframe level. since the maximum fas word error count in a one second peri od is 4000, this counter cannot saturate. fascr1: fas error count register 1 (address=02 hex) fascr2: fas error count register 2 (address=04 hex) (msb) (lsb) fas11 fas10 fas9 fas8 fas7 fas6 (note 2) (note 2) fascr1 fas5 fas4 fas3 fas2 fas1 fas0 (note 1) (note 1) fascr2 symbol position name and description fas11 fascr1.7 msb of the 12?bit fas error count fas0 fascr2.2 lsb of the 12?bit fas error count notes: 1. the lower two bits of fascr1 at address 02 are the most significant bits of the 10?bit crc4 error counter. 2. the lower two bits of fascr2 at address 04 are th e most significant bits of the 10?bit e?bit counter. 9 ds0 monitoring function each framer in the ds21354/554 has the ability to monitor one ds0 (64kbps) channel in the transmit direction and one ds0 channel in the receive directi on at the same time. in the transmit direction the user will determine which channel is to be monitored by properly setting the tcm0 to tcm4 bits in the ccr4 register. in the receive direction, the rcm0 to rcm4 b its in the ccr5 register need to be properly set. the ds0 channel pointed to by the tcm0 to tcm4 bits will appear in the transmit ds0 monitor (tds0m) register and the ds0 channe l pointed to by the rcm0 to rcm4 bits will appear in the receive ds0 (rds0m) register. th e tcm4 to tcm0 and rcm4 to rcm0 b its should be programmed with the decimal decode of the appropriate e1 channel.
ds21354 & DS21554 47 of 117 for example, if ds0 channel 6 in the transmit direction and ds0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into ccr5 and ccr6: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0 ccr4: common control register 4 (address=a8 hex) [repeated here from section 6 for convenience] (msb) (lsb) rlb llb liais tcm4 tcm3 tcm2 tcm1 tcm0 symbol position name and description rlb ccr4.7 remote loopback. llb ccr4.6 local loopback. liais ccr4.5 line interface ais generation enable. tcm4 ccr4.4 transmit channel monitor bit 4. msb of a channel decode that determines which transmit channel data will appear in the tds0m register. see section 9 for details. tcm3 ccr4.3 transmit channel monitor bit 3. tcm2 ccr4.2 transmit channel monitor bit 2. tcm1 ccr4.1 transmit channel monitor bit 1. tcm0 ccr4.0 transmit channel monitor bit 0. lsb of the channel decode. tds0m: transmit ds0 monito r register (address=a9 hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbol position name and description b1 tds0m.7 transmit ds0 channel bit 1. msb of the ds0 channel (first bit to be transmitted). b2 tds0m.6 transmit ds0 channel bit 2. b3 tds0m.5 transmit ds0 channel bit 3. b4 tds0m.4 transmit ds0 channel bit 4. b5 tds0m.3 transmit ds0 channel bit 5. b6 tds0m.2 transmit ds0 channel bit 6. b7 tds0m.1 transmit ds0 channel bit 7. b8 tds0m.0 transmit ds0 channel bit 8. lsb of the ds0 channel (last bit to be transmitted).
ds21354 & DS21554 48 of 117 ccr5: common control register 5 (address=aa hex) [repeated here from section 6 for convenience] (msb) (lsb) lirst resalgn tesalgn rcm4 rcm3 rcm2 rcm1 rcm0 symbol position name and description lirst ccr5.7 line interface reset. resalgn ccr5.6 receive elastic store align. tesalgn ccr5.5 transmit elastic store align. rcm4 ccr5.4 receive channel monitor bit 4. msb of a channel decode that deter- mines which receive channel data will appear in the rds0m register. see section 9 for details. rcm3 ccr5.3 receive channel monitor bit 3. rcm2 ccr5.2 receive channel monitor bit 2. rcm1 ccr5.1 receive channel monitor bit 1. rcm0 ccr5.0 receive channel monitor bit 0. lsb of the channel decode. rds0m: receive ds0 monitor register (address=ab hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbol position name and description b1 rds0m.7 receive ds0 channel bit 1. msb of the ds0 channel (first bit received). b2 rds0m.6 receive ds0 channel bit 2. b3 rds0m.5 receive ds0 channel bit 3. b4 rds0m.4 receive ds0 channel bit 4. b5 rds0m.3 receive ds0 channel bit 5. b6 rds0m.2 receive ds0 channel bit 6. b7 rds0m.1 receive ds0 channel bit 7. b8 rds0m.0 receive ds0 channel bit 8. lsb of the ds0 channel (last bit received). 10 signaling operation the ds21354/554 contains provisions for both processor based (i.e., softwa re based) signaling bit access and for hardware based access. both the processo r based access and the hardware based access can be used simultaneously if necessary. the processor ba sed signaling is covere d in section 10.1 and the hardware based signaling is covered in section 10.2. when referring to signaling, the voice channel numbering scheme is used. 10.1 processor based signaling the channel associated signaling (cas) bits embedded in the e1 stream can be extracted from the receive stream and inserted into th e transmit stream by the framer. each of the 30 voice channels has four signaling bits (a/b/c/d) associated with it. the numbers in parenthesis () are the voice channel associated with a particular signaling bit. the voice channel numbers have been assigned as described in the itu documents. please note that this is different than the channel numbering scheme (1 to 32) that is used in the rest of the data sheet.
ds21354 & DS21554 49 of 117 for example, voice channel 1 is associated with timeslot 1 (channel 2) and voice channel 30 is associated with timeslot 31 (channel 32). there is a set of 16 registers for the receive side (rs1 to rs16) and 16 registers on the transmit side (ts1 to ts16). the signaling registers are detailed below. rs1 to rs16: receive signaling registers (address=30 to 3f hex ) (msb) (lsb) 0 0 0 0 x y x x rs1 (30) a(1) b(1) c(1) d(1) a(16) b(16) c(16) d(16) rs2 (31) a(2) b(2) c(2) d(2) a(17) b(17) c(17) d(17) rs3 (32) a(3) b(3) c(3) d(3) a(18) b(18) c(18) d(18) rs3 (33) a(4) b(4) c(4) d(4) a(19) b(19) c(19) d(19) rs5 (34) a(5) b(5) c(5) d(5) a(20) b(20) c(20) d(20) rs6 (35) a(6) b(6) c(6) d(6) a(21) b(21) c(21) d(21) rs7 (36) a(7) b(7) b(7) b(7) b(22) b(22) b(22) b(22) rs8 (37) a(8) b(8) c(8) d(8) a(23) b(23) c(23) d(23) rs9 (38) a(9) b(9) c(9) d(9) a(24) b(24) c(24) d(24) rs10 (39) a(10) b(10) c(10) d(10) a(25) b(25) c(25) d(25) rs11 (3a) a(11) b(11) c(11) d(11) a(26) b(26) c(26) d(26) rs12 (3b) a(12) b(12) c(12) d(12) a(27) b(27) c(27) d(27) rs13 (3c) a(13) b(13) c(13) d(13) a(28) b(28) c(28) d(28) rs14 (3d) a(14) b(14) c(14) d(14) a(29) b(29) c(29) d(29) rs15 (3e) a(15) b(15) c(15) d(15) a(30) b(30) c(30) d(30) rs16 (3f) symbol position name and description x rs1.0/1/3 spare bits. y rs1.2 remote alarm bit (integ rated and reported in sr1.6). a(1) rs2.7 1. signaling bit a for channel 1 d(30) rs16.0 signaling bit d for channel 30. each receive signaling register (rs1 to rs16) re ports the incoming signaling from two timeslots. the bits in the receive signaling registers are updated on multiframe boundaries so the user can utilize the receive multiframe interrupt in the receive status register 2 (sr2.7) to know when to retrieve the signaling bits. the user has a full 2 ms to retrieve the signaling bits before the data is lost. the rs registers are updated under all conditions. their validity should be qualified by checking for synchronization at the cas level. in ccs signaling mode, rs1 to rs 16 can also be used to extract signaling information. via the sr2.7 bit, the user will be informed when the signaling registers have been loaded with data. the user has 2 ms to retrieve the data before it is lost. the signaling data reported in rs1 to rs16 is also available at the rsig and rser pins. a change in the signaling bits from one multiframe to the next will cause the rsa1 (sr1.7) and rsa0 (sr1.5) status bits to be set at the same time. the user can enable the int* pin to toggle low upon detection of a change in signalin g by setting either the imr1.7 or imr1.5 bit. once a signaling change has been detected, the user has at least 1.75 ms to r ead the data out of the rs1 to rs16 registers before the data will be lost.
ds21354 & DS21554 50 of 117 ts1 to ts16: transmit signaling registers (address=40 to 4f hex) (msb) (lsb) 0000 xyxxts1 (40) a(1) b(1) c(1) d(1) a(16) b(16) c(16) d(16) ts2 (41) a(2) b(2) c(2) d(2) a(17) b(17) c(17) d(17) ts3 (42) a(3) b(3) c(3) d(3) a(18) b(18) c(18) d(18) ts4 (43) a(4) b(4) c(4) d(4) a(19) b(19) c(19) d(19) ts5 (44) a(5) b(5) c(5) d(5) a(20) b(20) c(20) d(20) ts6 (45) a(6) b(6) c(6) d(6) a(21) b(21) c(21) d(21) ts7 (46) a(7) b(7) b(7) b(7) b(22) b(22) b(22) b(22) ts8 (47) a(8) b(8) c(8) d(8) a(23) b(23) c(23) d(23) ts9 (48) a(9) b(9) c(9) d(9) a(24) b(24) c(24) d(24) ts10 (49) a(10) b(10) c(10) d(10) a(25) b(25) c(25) d(25) ts11 (4a) a(11) b(11) c(11) d(11) a(26) b(26) c(26) d(26) ts12 (4b) a(12) b(12) c(12) d(12) a(27) b(27) c(27) d(27) ts13 (4c) a(13) b(13) c(13) d(13) a(28) b(28) c(28) d(28) ts14 (4d) a(14) b(14) c(14) d(14) a(29) b(29) c(29) d(29) ts15 (4e) a(15) b(15) c(15) d(15) a(30) b(30) c(30) d(30) ts16 (4f) symbol position name and description x ts1.0/1/3 spare bits. y ts1.2 remote alarm bit (integ rated and reported in sr1.6). a(1) ts2.7 1. signaling bit a for channel 1 d(30) ts16.0 signaling bit d for channel 30. each transmit signaling register (ts1 to ts16) c ontains the cas bits for two timeslots that will be inserted into the outgoing stream if enabled to do so via tcr1.5. on multiframe boundaries, the framer will load the values present in the transmit signalin g register into an outgoing signaling shift register that is internal to the device. the user can utilize the transmit multiframe bit in status register 2 (sr2.5) to know when to update the signaling bits. the bit w ill be set every 2 ms and the user has 2 ms to update the tsr?s before the old data will be retransmitted. itu specifications recommend that the abcd signaling not be set to all zeros because they will emulate a cas multiframe alignment word. the ts1 register is special beca use it contains the cas multiframe alignment word in its upper nibble. the upper nibble must always be set to 0000 or else the terminal at the fa r end will lose multiframe synchronization. if the user wishes to transmit a multiframe alarm to the far end, then the ts1.2 bit should be set to a one. if no alarm is to be tran smitted, then the ts1.2 bit should be cleared. the three remaining bits in ts1 are the spare bits. if they are not used, they should be set to one. in ccs signaling mode, ts1 to ts16 can also be used to insert sign aling information. via the sr2.5 bit, the user will be informed when the signaling registers need to be loaded with data. the user has 2 ms to load the data before the old data will be retransmitted. via the ccr3.6 bit, the user has the option to use the transmit channel blocking registers (tcbrs) to determine on a channel by channel basis, which signaling bits are to be inserted via the tsrs (the corresponding bit in the tcbrs = 1) and which are to be sourced from the tser or tsig pin (the corresponding bit in the tcbrs = 0). see figure 19-15 for more details.
ds21354 & DS21554 51 of 117 10.2 hardware based signaling 10.2.1 receive side in the receive side of the hardware based signaling, there are two operating modes for the signaling buffer; signaling extraction and si gnaling re?insertion. signaling extr action involves pulling the signaling bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in a serial pcm fashion on a channel?by ?channel basis at the rsig output. this mode is always enabled. in this mode, the receive elastic store may be enabled or disabled. if the receive elastic store is enabled, then the backplane clock (rsysclk) must be 2.048/4.096/ 8.192 mhz. the abcd signaling bits are output on rsig in the lower nibble of each channel. the rs ig data is updated once a multiframe (2 ms) unless a freeze is in effect. see the timing diagra ms in section 19.1 for some examples. the other hardware based signaling operating mode called signaling re?insertion can be invoked by setting the rsre control bit high (ccr3.3 = 1). in th is mode, the user will provide a multiframe sync at the rsync pin and the signaling data be re?aligned at the rser output according to this applied multiframe boundary. in this mode, the elastic stor e must be enabled the backplane clock must be 2.048/4.096/8.192 mhz. the signaling data in the two multiframe buffer w ill be frozen in a known good state upon either a loss of synchronization (oof event), carrier loss, or frame slip. to allow this freeze action to occur, the rfe control bit (ccr2.0) should be set high. the user can force a freeze by setting the rff control bit (ccr2.1) high. setting the rff bit high causes the sa me freezing action as if a loss of synchronization, carrier loss, or slip has occurred. the 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the rsig pin (and at the rser pin if rsre = 1 via ccr3.3). when freezing is enabled (rfe = 1), the signaling data will be he ld in the last known good state until the corrupting error condition subsides. when the error condition sub-sides, the signaling data will be held in the old state for an additional 3 ms to 5 ms before being allowed to be updated with ne w signaling data. 10.2.2 transmit side via the thse control bit (ccr3.2), the ds21354/554 can be set up to take the si gnaling data presented at the tsig pin and insert the signaling data into the pcm data stream that is being input at the tser pin. the hardware signaling insertion capabilities of each framer are available whether the transmit side elastic store is enabled or disabled. if the transmit side elastic store is enabled, the backplane clock (tsysclk) must be 2.048/4.096/8.192 mhz. when hardware signaling insertion is enabled on a framer (thse = 1), then the user must enable the transmit channel blocking register function select (tcbfs) control bit (ccr3.6 = 1). this is needed so that the cas multiframe alignment word, multiframe remote alarm, and spare bits can be added to timeslot 16 in frame 0 of the multiframe. the ts1 register should be programmed with the proper information. if ccr3.6 = 1, then a zero in the tcbrs implies that signaling data is to be sourced from tser (or tsig if ccr3.2 = 1) and a one implies that si gnaling data for that channel is to be sourced from the transmit signaling (ts) registers. see definition below.
ds21354 & DS21554 52 of 117 tcbr1/tcbr2/tcbr3/tcbr4: definition when ccr3.6=1 (msb) (lsb) ch18 ch3 ch17 ch2 ch16 ch1 1* 1* tcbr1(22) ch22 ch7 ch21 ch6 ch20 ch5 ch19 ch4 tcbr2(23) ch26 ch11 ch25 ch10 ch24 ch9 ch23 ch8 tcbr3(24) ch30 ch15 ch29 ch14 ch28 ch13 ch27 ch12 tcbr4(25) * these bits should be set to one to allow the in ternal ts1 register to create the cas multiframe alignment word and spare/remote alarm bits. the user can also take advantage of this functionality to intermix signaling data from the tsig pin and from the internal transmit signaling registers (ts1 to ts16). as an example, assume that the user wishes to source all the signaling data except for voice channels 5 and 10 from the tsig pin. in this application, the following bits and regi sters would be programmed as follows: control bits register values thse = 1 (ccr3.2) ts1 = 0bh (mf alignment word, remote alarm etc.) tcbfs = 1 (ccr3.6) tcbr1 = 03h (source timeslot 16, frame 1 data) t16s = 0 (tcr1.5) tcbr2 = 01h (source voice channel 5 signaling data from ts6) cbr3 = 04h (source voice channel 10 signaling data from ts11) tcbr4 = 00h 11 per?channel code generation and loopback the ds21354/554 can replace data on a channel?by?c hannel basis in both the transmit and receive directions. the transmit direction is from the backplan e to the e1 line and is covered in section 11.1. the receive direction is from the e1 line to th e backplane and is covered in section 11.2. 11.1 transmit side code generation in the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. the first met hod which is covered in section 11.1.1 was a feature contained in the original ds2153 while th e second method which is covered in 11.1.2 is a new feature of the ds2154/354/554. 11.1.1 simple idle code insertion and per?channel loopback the first method involves using the transmit idle regi sters (tir1/2/3/4) to determine which of the 32 e1 channels should be overwritten with the code placed in the transmit idle definition register (tidr). this method allows the same 8?bit c ode to be placed into any of the 32 e1 channels. if this method is used, then the ccr3.5 control bit must be set to zero. each of the bit position in the transmit idle registers (tir1/tir2/tir3/tir4) represent a ds0 channel in the outgoing frame. when these bits are set to a one, the corresponding channel will transmit the idle code contained in the transmit idle definition register (tidr). the transmit idle registers (tirs) have an alternate function that allow them to define a per?channel loopback (pclb). if the tirfs control bit (ccr3.5) is set to one, then the tirs will determine which channels (if any) from the backplan e should be replaced with the data from the receive side or in other words, off of the e1 line. if this mode is enable d, then transmit and receive clocks and frame syncs must be synchronized.
ds21354 & DS21554 53 of 117 one method to accomplish this would be to tie rclk to tclk and rfsync to tsync. there are no restrictions on which channels can be looped back or on how many channels can be looped back. tir1/tir2/tir3: transmit idle registers (address=26 to 29 hex) [also used for per?channel loopback] (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tir1 (26) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tir2 (27) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tir3 (28) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 tir4 (29) symbols positions name and description ch1 - 32 tir1.0 - 4.7 transmit idle code in sertion control bits. 0 = do not insert the idle code in the tidr into this channel 1 = insert the idle code in the tidr into this channel note: if ccr3.5 = 1, then a zero in the tirs implies that channel data is to be sourced from tser and a one implies that channel data is to be sourced from the output of the receive side framer (i.e., per?channel loopback; see figure 3-1). tidr: transmit idle definiti on register (address=2a hex) (msb) (lsb) tidr7 tidr6 tidr5 tidr4 tidr3 tidr2 tidr1 tidr0 symbol position name and description tidr7 tidr.7 msb of the idle code (this bit is transmitted first) tidr0 tidr.0 lsb of the idle code (this bit is transmitted last) 11.1.2 per?channel code insertion the second method involves using the transmit channe l control registers (tcc1 /2/3/4) to determine which of the 32 e1 channels shoul d be overwritten with the code placed in the transmit channel registers (tc1 to tc32). this method is more flexible than the first in that it allows a different 8?bit code to be placed into each of the 32 e1 channels. tc1 to tc32: transmit channel registers (address=60 to 7f hex) (for brevity, only channel one is shown; see for other register address) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 tc1 (60) symbol position name and description c7 tc1.7 msb of the code (this bit is transmitted first) c0 tc1.0 lsb of the code (this bit is transmitted last)
ds21354 & DS21554 54 of 117 tcc1/tcc2/tcc3/tcc4: transmit channel control register (address=a0 to a3 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tcc1 (a0) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tcc2 (a1) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tcc3 (a2) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 tcc4 (a3) symbol position name and description ch 1 - 32 tcc1.0 - 4.7 transmit channel code insertion control bits 0 = do not insert data from the tc register into the transmit data stream 1 = insert data from the tc register into the transmit data stream 11.2 receive side code generation on the receive side, the receive channel control registers (rcc1/2/3/4) are used to determine which of the 32 e1 channels off of the e1 line and going to the backplane should be overwritten with the code placed in the receive channel registers (rc1 to rc 32). this method allows a different 8?bit code to be placed into each of the 32 e1 channels. rc1 to rc32: receive channel registers (address = 80 to 9f hex) (for brevity, only channel one is shown; see table 5-1 for other register address) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 rc1 (80) symbol position name and description c7 rc1.7 msb of the code (this bit is sent first to the backplane) c0 rc1.0 lsb of the code (this bit is sent last to the backplane) rcc1/rcc2/rcc3/rcc4: receive channel control register (address = a4 to a7 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rcc1 (a4) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rcc2 (a5) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rcc3 (a6) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 rcc4 (a7) symbol position name and description ch1 - 32 rcc1.0 ? 4.7 receive channel code insertion control bits 0 = do not insert data from the rc1 re gister into the receive data stream 1 = insert data from the rc1 register into the receive data stream 12 clock blocking registers the receive channel blocking registers (rcbr1 / rcbr2 / rcbr3 / rcbr4) and the transmit channel blocking registers (tcbr1 / tcbr2 / tcbr3 / tcbr4) control rchblk and tchblk pins respectively. (the rchblk and tchblk pins are us er programmable outputs that can be forced either high or low during individual channels). these outputs can be used to block clocks to a usart or lapd controller in isdn?pri applications.
ds21354 & DS21554 55 of 117 when the appropriate bits are set to a one, the rchblk and tchblk pin will be held high during the entire corresponding channel time. see the timing in section 19 for an ex ample. the tcbrs have alternate mode of use. via the ccr3.6 bit, the user has the option to use the tcbrs to determine on a channel by channel basis, which sign aling bits are to be inserted via the tsrs (the corresponding bit in the tcbrs = 1) and which are to be sourced from th e tser or tsig pins (the corresponding bit in the tcbr = 0). see the timing in section 19.2 for an example. rcbr1/rcbr2/rcbr3/rcbr4: rece ive channel blocking registers (address=2b to 2e hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rcbr1 (2b) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rcbr2 (2c) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rcbr3 (2d) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 rcbr4 (2e) symbols positions name and description ch1 - 32 rcbr1.0 - 4.7 receive channel blocking control bits. 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time tcbr1/tcbr2/tcbr3/tcbr4: transmit channel blocking registers (address=22 to 25 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tcbr1 (22) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tcbr2 (23) ch24 ch23 ch22 ch21 ch20 ch 19 ch18 ch17 tcbr3 (24) ch32 ch31 ch30 ch29 ch28 ch 27 ch26 ch25 tcbr4 (25) symbols positions name and description ch1 - 32 tcbr1.0 - 4.7 transmit channel blocking control bits. 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time note: if ccr3.6 = 1, then a zero in the tcbrs implies that si gnaling data is to be sourced from tser (or tsig if ccr3.2 = 1) and a one implies that signaling data for that channel is to be sourced from the transmit signaling (ts) registers. in this mode, the voice ch annel numbering scheme (ch1 ? ch30) is used. see definition below. tcbr1/tcbr2/tcbr3/tcbr4: definition when ccr3.6=1 (msb) (lsb) ch18 ch3 ch17 ch2 ch16 ch1 1* 1* tcbr1(22) ch22 ch7 ch21 ch6 ch20 ch5 ch19 ch4 tcbr2(23) ch26 ch11 ch25 ch10 ch24 ch9 ch23 ch8 tcbr3(24) ch30 ch15 ch29 ch14 ch28 ch13 ch27 ch12 tcbr4(25) * these bits should be set to one to allow the in ternal ts1 register to create the cas multiframe alignment word and spare/remote alarm bits.
ds21354 & DS21554 56 of 117 13 elastic stores operation the ds21354/554 contains dual two?frame (512 bits) elastic stores, one for the receive direction, and one for the transmit direction. these elastic stores have two main purposes. first, they can be used to rate convert the e1 data stream to 1.544 mbps (or a mu ltiple of 1.544 mbps) which is the t1 rate. secondly, they can be used to absorb the differences in frequency and phase between the e1 data stream and an asynchronous (i.e., not frequency locked) bac kplane clock which can be 1.544 mhz or 2.048/4.096/8.192 mhz. the backplane clock can burst at rates up to 8.192 mhz. both elastic stores contain full controlled slip capability which is necessary for this second pur pose. the elastic stores can be forced to a known depth via the elastic store reset bits (ccr6.0 & ccr 6.1). toggling these bits forces the read and write pointers into opposite frames. both el astic stores within a framer are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to them. the transmit side elastic store can be enabled whether the receive elastic store is enabled or disabled and vice versa. al so, each elastic store can interface to either a 1.544 mhz or 2.048/4.096/8.192 mhz b ackplane without regard to the backplane rate the other elastic store is interfacing. 13.1 receive side if the receive side elastic store is enabled (rcr 2.1=1), then the user must provide either a 1.544 mhz (rcr2.2 =0) or 2.048/4.096/8.192 mhz (rcr2.2 = 1) cloc k at the rsysclk pin. the user has the option of either providing a fram e/multiframe sync at the rsync pin (rcr1.5 = 1) or having the rsync pin provide a pulse on frame/multiframe boundaries (rcr1.5 = 0). if the user wishes to obtain pulses at the frame boundary, then rcr1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe boundary, then rcr1.6 must be set to one. the ds21354/554 will always indicate frame boundaries via the rfsync output whether the elastic store is enable d or not. if the elastic store is enabled, then either cas (rcr1.7 = 0) or crc4 ( rcr1.7 = 1) multiframe boundaries will be indicated via the rmsync output. if the user selects to a pply a 1.544 mhz clock to the rsysclk pin, then every fourth channel of the received e1 data will be dele ted and a f?bit position (which will be forced to one) will be inserted. hence cha nnels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received e1 data stream. also, in 1.544 mhz applications, the rchblk output will not be active in channels 25 through 32 (or in other words, rcbr4 is not active). see section 19.1 for timing details. if the 512?bit elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties, then a full frame of data (256?bits) will be repeated at rser and the sr1.4 and rir.3 bits will be set to a one. if the buffer fills, then a full frame of data will be deleted and the sr1.4 and rir.4 bits will be set to a one. 13.2 transmit side the operation of the transmit elastic store is very similar to the receive side. the transmit side elastic store is enabled via ccr3.7. a 1.544 mhz (ccr3.1 = 0) or 2.048/4.096/8.192 mhz (ccr3.1 = 1) clock can be applied to the tsysclk i nput. the tsysclk can be a bursty clock with rates up to 8.192 mhz. the user must supply either an 8 khz frame sync pul se or a multiframe sync pulse to the tssync input. see section 19.2 for timing details. controlled slips in the transmit elastic store are reported in the sr2.0 bit and the direction of the slip is reported in the rir.6 and rir.7 bits. 14 additional (sa) and international (si) bit operation the ds21354/554 provides for access to both the sa and th e si bits via three diff erent methods. the first is via a hardware scheme using the rlink/rl clk and tlink/ tlclk pins. the first method is discussed in section 14.1. the second involves using the internal raf/rnaf and taf/tnaf registers and is discussed in section 14.2 th e third method which is covered in section 14.3 involves an expanded version of the second method and is one of the features added to the ds2154/354/554 from the original ds2153 definition.
ds21354 & DS21554 57 of 117 14.1 hardware scheme on the receive side, all of the received data is re ported at the rlink pin. via rcr2, the user can control the rlclk pin to pulse during any combination of sa bits. this allows the user to create a clock that can be used to capture the needed sa bits. if rs ync is programmed to output a frame boundary, it will identify the si bits. see section 19.1 for detailed timing. on the transmit side, the individual sa bits can be either sourced from the internal tnaf register (see section 14.2 for details) or from the external tlin k pin. via tcr2, the framer can be programmed to source any combination of the additional bits from the tlink pin. if the user wishes to pass the sa bits through the framer without them being altered, then th e device should be set up to source all five sa bits via the tlink pin and the tlink pin should be tied to the tser pin. si bits can be inserted through the tser pin via the clearing of the tcr1.3 bit. please see the timing diagrams and the transmit data flow diagram in section 19.2 for examples. 14.2 internal register scheme based on double?frame on the receive side, the raf and rnaf registers will always report the data as it received in the additional and international bit lo cations. the raf and rnaf regist ers are updated with the setting of the receive align frame bit in status register 2 (sr2.6). the host can use the sr2.6 bit to know when to read the raf and rnaf registers. it has 250 us to retrieve the data before it is lost. on the transmit side, data is sampled from the taf and tnaf registers with the setting of the transmit align frame bit in status register 2 (sr2.3). the host can use the sr2.3 bit to know when to update the taf and tnaf registers. it has 250 us to update the data or else the old data will be retransmitted. data in the si bit position will be overwritten if either the framer is programmed: (1) to source the si bits from the tser pin, (2) in the crc4 mode, or (3) have automatic e?bit insertion enabled. data in the sa bit position will be overwritten if any of the tcr2.3 to tcr2.7 bits are set to one (please see section 14.1 for details). please see the register descriptions fo r tcr1 and tcr2 and figure 19-15 for more details. raf: receive align frame register (address=2f hex) (msb) (lsb) si0011011 symbol position name and description si raf.7 international bit. 0raf.6 frame alignment signal bit. 0raf.5 frame alignment signal bit. 1raf.4 frame alignment signal bit. 1raf.3 frame alignment signal bit. 0raf.2 frame alignment signal bit. 1raf.1 frame alignment signal bit. 1raf.0 frame alignment signal bit.
ds21354 & DS21554 58 of 117 rnaf: receive non?align fram e register (address=1f hex) (msb) (lsb) si 1 a sa4 sa5 sa6 sa7 sa8 symbol position name and description si rnaf.7 international bit. 1 rnaf.6 frame non?alignment signal bit. a rnaf.5 remote alarm. sa4 rnaf.4 additional bit 4. sa5 rnaf.3 additional bit 5. sa6 rnaf.2 additional bit 6. sa7 rnaf.1 additional bit 7. sa8 rnaf.0 additional bit 8. taf: transmit align frame register (address=20 hex) (msb) (lsb) si0011011 symbol position name and description si taf.7 international bit. 0taf.6 frame alignment signal bit. 0taf.5 frame alignment signal bit. 1taf.4 frame alignment signal bit. 1taf.3 frame alignment signal bit. 0taf.2 frame alignment signal bit. 1taf.1 frame alignment signal bit. 1taf.0 frame alignment signal bit. note: the taf register must be programmed with the seven bit fas word; the ds21354/554 does not automatically set these bits tnaf: transmit non?align frame register (address=21 hex) (msb) (lsb) si 1 a sa4 sa5 sa6 sa7 sa8 symbol position name and description si tnaf.7 international bit. 1 tnaf.6 frame non?alignment signal bit. a tnaf.5 remote alarm (used to transmit the alarm). sa4 tnaf.4 additional bit 4. sa5 tnaf.3 additional bit 5. sa6 tnaf.2 additional bit 6. sa7 tnaf.1 additional bit 7. sa8 tnaf.0 additional bit 8.
ds21354 & DS21554 59 of 117 note: bit 2 of the tnaf register must be programmed to one; the ds21354/554 does not automatically set this bit 14.3 internal register scheme based on crc4 multiframe on the receive side, there is a set of eight registers (rsiaf, rsinaf, rra, rsa4 to rsa8) that report the si and sa bits as they are received. these regist ers are updated with the setting of the receive crc4 multiframe bit in status register 2 (sr2.1). the hos t can use the sr2.1 bit to know when to read these registers. the user has 2 ms to retrieve the data before it is lost. the msb of each register is the first received. please see the register descriptions below for more details. on the transmit side, there is also a set of eight registers (tsiaf, tsinaf, tra, tsa4 to tsa8) that via the transmit sa bit control register (tsacr), can be programmed to insert both si and sa data. data is sampled from these registers with the setting of the tr ansmit multiframe bit in st atus register 2 (sr2.5). the host can use the sr2.5 bit to know when to update th ese registers. it has 2 ms to update the data or else the old data will be retransmitted. the msb of each register is the first bit transmitted. please see the register descriptions below a nd figure 19-15 for more details. register address (hex) function rsiaf 58 the eight si bits in the align frame rsinaf 59 the eight si bits in the non?align frame rra 5a the eight reportings of the receive remote alarm (ra) rsa4 5b the eight sa4 reported in each crc4 multiframe rsa5 5c the eight sa5 reported in each crc4 multiframe rsa6 5d the eight sa6 reported in each crc4 multiframe rsa7 5e the eight sa7 reported in each crc4 multiframe rsa8 5f the eight sa8 reported in each crc4 multiframe tsiaf 50 the eight si bits to be inserted into the align frame tsinaf 51 the eight si bits to be inserted into the non?align frame tra 52 the eight settings of remote alarm (ra) tsa4 53 the eight sa4 settings in each crc4 multiframe tsa5 54 the eight sa5 settings in each crc4 multiframe tsa6 55 the eight sa6 settings in each crc4 multiframe tsa7 56 the eight sa7 settings in each crc4 multiframe tsa8 57 the eight sa8 settings in each crc4 multiframe tsacr: transmit sa bit control register (address=1c hex) (msb) (lsb) siaf sinaf ra sa4 sa5 sa6 sa7 sa8 symbol position name and description siaf tsacr.7 international bit in align frame insertion control bit. 0 = do not insert data from the tsiaf register into the transmit data stream 1 = insert data from the tsiaf register into the transmit data stream
ds21354 & DS21554 60 of 117 symbol position name and description sinaf tsacr.6 international bit in non?align frame insertion control bit. 0 = do not insert data from the tsinaf register into the transmit data stream 1 = insert data from the tsinaf register into the transmit data stream ra tsacr.5 remote alarm insertion control bit. 0 = do not insert data from the tra register into the transmit data stream 1 = insert data from the tra register into the transmit data stream sa4 tsacr.4 additional bit 4 insertion control bit. 0 = do not insert data from the tsa4 register into the transmit data stream 1 = insert data from the tsa4 register into the transmit data stream sa5 tsacr.3 additional bit 5 insertion control bit. 0 = do not insert data from the tsa5 register into the transmit data stream 1 = insert data from the tsa5 register into the transmit data stream sa6 tsacr.2 additional bit 6 insertion control bit. 0 = do not insert data from the tsa6 register into the transmit data stream 1 = insert data from the tsa6 register into the transmit data stream sa7 tsacr.1 additional bit 7 insertion control bit. 0 = do not insert data from the tsa7 register into the transmit data stream 1 = insert data from the tsa7 register into the transmit data stream sa8 tsacr.0 additional bit 8 insertion control bit. 0 = do not insert data from the tsa8 register into the transmit data stream 1 = insert data from the tsa8 register into the transmit data stream 15 hdlc controller for the sa bits or ds0 the ds21354/554 has the ability to extract/insert data from/into the sa bit positions (sa4 to sa8) or from/to any multiple of ds0 or sub ds0 channels. the sct contains a complete hdlc controller and this operation is c overed in section 15.1. 15.1 general overview the ds21354/554 contains a complete hdlc controlle r with 64?byte buffers in both the transmit and receive directions the hdlc controller performs all the necessary overhead for generating and receiving an hdlc formatted message. the hdlc controller automatically generates and detects flags, generates and checks the crc check sum, generates and detects abort sequences, stuffs and destuffs ze ros (for transparency), and byte aligns to the hdlc data stream. there are eleven registers that the host will use to operate and control the operation of the hdlc controller. a brief description of the registers is shown in table 15.1.
ds21354 & DS21554 61 of 117 hdlc controller register list table 15-1 name function hdlc control register (hcr) hdlc status register (hsr) himr interrupt mask register (himr) general control over the hdlc controller key status information for both transmit and receive directions allows/stops stat us bits to/from causing an interrupt receive hdlc information register (rhir) receive hdlc fifo register (rhfr) receive hdlc ds0 control register 1 (rdc1) receive hdlc ds0 control register 2 (rdc2) status information on receive hdlc controller access to 64?byte hdlc fifo in receive direction controls the hdlc function when used on ds0 channels controls the hdlc function when used on ds0 channels transmit hdlc information register (thir) transmit hdlc fifo register (thfr) transmit hdlc ds0 control register 1 (tdc1) transmit hdlc ds0 control register 2 (tdc2) status information on transmit hdlc controller access to 64?byte hdlc fifo in transmit direction controls the hdlc function when used on ds0 channels controls the hdlc function when used on ds0 channels 15.2 hdlc status registers three of the hdlc controller registers (hsr, rhir , and thir) provide status information. when a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. some of the bits in these three status registers are latched and some are real time bits that are not latched. section 15.4 contains regi ster descriptions that list which bits are latched and which are not. with the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again. the real time bits report the current instantane ous conditions that are occurring and the history of these bits is not latched. like the other status registers in the framer, the user will always proceed a read of any of the three registers with a write. the byte written to the register will inform the framer which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). the user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wi sh to obtain the latest information on. when a one is written to a bit location, the read register will be upda ted with current value and it will be cleared. when a zero is written to a bit position, the read register w ill not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. this write?read?write (for polled driven access) or write?read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. this operation is key in controlling the ds21354/554 with higher?order software languages.
ds21354 & DS21554 62 of 117 like the sr1 and sr2 status registers, the hsr register has the unique ability to initiate a hardware interrupt via the int* output pin. each of the events in the hsr can be either masked or unmasked from the interrupt pin via the hdlc interrupt mask register (himr). interrupts will force the int* pin low when the event occurs. the int pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. 15.3 basic operation details as a basic guideline for interpreting and sending hdlc messages, the following sequences can be applied: 15.3.1 receive a hdlc message 1. enable rps interrupts 2. wait for interrupt to occur 3. disable rps interrupt and enable e ither rpe, rne, or rhalf interrupt 4. read rhir to obtain rempty status a. if rempty=0, then record obyte, cbyte, and pok bits and then read the fifo a1. if cbyte=0 then skip to step 5 a2. if cbyte=1 then skip to step 7 b. if rempty=1, then skip to step 6 5. repeat step 4 6. wait for interrupt, skip to step 4 7. if pok=0, then discard whole pa cket, if pok=1, accept the packet a. disable rpe, rne, or rhalf interrupt, enab le rps interrupt and return to step 1. 15.3.2 transmit an hdlc message 1. make sure hdlc controller is done sending any previous messages and is current sending flags by checking that the fifo is empty by reading the tempty status bit in the thir register 2. enable either the thalf or tnf interrupt 3. read thir to obtain tfull status a. if tfull=0, then write a byte into the fifo and skip to next step (special case occurs when the last byte is to be written, in this case set teom=1 before writing the byte and then skip to step 6) b. if tfull=1, then skip to step 5 4. repeat step 3 5. wait for interrupt, skip to step 3 6. disable thalf or tnf interrupt and enable tmend interrupt 7. wait for an interrupt, then read tudr status bit to make sure packet was transmitted correctly.
ds21354 & DS21554 63 of 117 15.4 hdlc register description hcr: hdlc control register (address=b0 hex) (msb) (lsb) ? rhr tfs thr tabt teom tzsd tcrcd symbol position name and description ? hcr.7 not assigned. should be set to zero when written. rhr hcr.6 receive hdlc reset. a 0 to 1 transition will reset the hdlc controller. must be cleared and set again for a subsequent reset. tfs hcr.5 transmit flag/idle select. 0 = 7eh 1 = ffh thr hcr.4 transmit hdlc reset. a 0 to 1 transition will reset the hdlc controller. must be cleared and set again for a subsequent reset. tabt hcr.3 transmit abort. a 0 to 1 transition will cause the fifo contents to be dumped and one feh abort to be sent followed by 7eh or ffh flags/idle until a new packet is initiated by writing new data into the fifo. must be cleared and set again for a s ubsequent abort to be sent. teom hcr.2 transmit end of message. should be set to a one ju st before the last data byte of a hdlc packet is written into the transmit fifo at thfr. this bit will be cleared by the hdlc controller when the last byte has been transmitted. tzsd hcr.1 transmit zero stuffer defeat. overrides internal enable. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer tcrcd hcr.0 transmit crc defeat. 0 = enable crc generation (normal operation) 1 = disable crc generation hsr: hdlc status register (address=b1 hex) (msb) (lsb) frcl rpe rps rhalf rne thalf tnf tmend symbol position name and description frcl hsr.7 framer receive carrier loss. set when 255 (or 2048 if ccr3.0 = 1) consecutive zeros have been detected at rposi and rnegi. rpe hsr.6 receive packet end. set when the hdlc controller detects either the finish of a valid message (i.e., crc check complete) or when the controller has experienced a message fault such as a crc checking error, or an overrun condition, or an abort ha s been seen. the setting of this bit prompts the user to read the rhir register for details. rps hsr.5 receive packet start . set when the hdlc controller detects an opening byte. the setting of this bit prompts the user to read the rhir register for details.
ds21354 & DS21554 64 of 117 symbol position name and description rhalf hsr.4 receive fifo half full. set when the receive 64?byte fifo fills beyond the half way point. the setting of this bit prompts the user to read the rhir register for details. rne hsr.3 receive fifo not empty. set when the receive 64?byte fifo has at least one byte available for a read. the setting of this bit prompts the user to read the rhir register for details. thalf hsr.2 transmit fifo half empty. set when the transmit 64?byte fifo empties beyond the half way point. the setting of this bit prompts the user to read the thir register for details. tnf hsr.1 transmit fifo not full. set when the transmit 64?byte fifo has at least one byte available. the setting of this bit prompts the user to read the thir register for details. tmend hsr.0 transmit message end. set when the transmit hdlc controller has finished sending a message. the setting of this bit prompts the user to read the thir register for details. note: the rpe, rps, and tmend bits are latched and will be cleared when read. himr: hdlc interrupt mask register (address=b2 hex) (msb) (lsb) frcl rpe rps rhalf rne thalf tnf tmend symbol position name and description frcl himr.7 framer receive carrier loss. 0 = interrupt masked 1 = interrupt enabled rpe himr.6 receive packet end. 0 = interrupt masked 1 = interrupt enabled rps himr.5 receive packet start. 0 = interrupt masked 1 = interrupt enabled rhalf himr.4 receive fifo half full. 0 = interrupt masked 1 = interrupt enabled rne himr.3 receive fifo not empty. 0 = interrupt masked 1 = interrupt enabled thalf himr.2 transmit fifo half empty. 0 = interrupt masked 1 = interrupt enabled tnf himr.1 transmit fifo not full. 0 = interrupt masked 1 = interrupt enabled
ds21354 & DS21554 65 of 117 symbol position name and description tmend himr.0 transmit message end. 0 = interrupt masked 1 = interrupt enabled rhir: receive hdlc information register (address=b3 hex) (msb) (lsb) rabt rcrce rovr rvm rempty pok cbyte obyte symbol position name and description rabt rhir.7 abort sequence detected. set whenever the hdlc controller sees 7 or more ones in a row. rcrce rhir.6 crc error. set when the crc checksum is in error. rovr rhir.5 overrun. set when the hdlc controller has attempted to write a byte into an already full receive fifo. rvm rhir.4 valid message. set when the hdlc controller has detected and checked a complete hdlc packet. rempty rhir.3 empty. a real?time bit that is set high when the receive fifo is empty. pok rhir.2 packet ok. set when the byte available for reading in the receive fifo at rhfr is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the crc was correct). cbyte rhir.1 closing byte. set when the byte available for reading in the receive fifo at rhfr is the last byte of a message (whether the message was valid or not). obyte rhir.0 opening byte. set when the byte available for reading in the receive fifo at rhfr is the first byte of a message. note: the rabt, rcrce, rovr, and rvm bits are latched and will be cleared when read. rhfr: receive hdlc fifo register (address=b4 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbol position name and description hdlc7 rhfr.7 hdlc data bit 7 . msb of a hdlc packet data byte. hdlc6 rhfr.6 hdlc data bit 6. hdlc5 rhfr.5 hdlc data bit 5. hdlc4 rhfr.4 hdlc data bit 4. hdlc3 rhfr.3 hdlc data bit 3. hdlc2 rhfr.2 hdlc data bit 2. hdlc1 rhfr.1 hdlc data bit 1. hdlc0 rhfr.0 hdlc data bit 0. lsb of a hdlc packet data byte.
ds21354 & DS21554 66 of 117 thir: transmit hdlc information register (address=b6 hex) (msb) (lsb) ? ? ? ? ? tempty tfull tudr symbol position name and description ?thir.7 not assigned. could be any value when read. ?thir.6 not assigned. could be any value when read. ?thir.5 not assigned. could be any value when read. ?thir.4 not assigned. could be any value when read. ?thir.3 not assigned. could be any value when read. tempty thir.2 transmit fifo empty. a real?time bit that is set high when the fifo is empty. tfull thir.1 transmit fifo full. a real?time bit that is set high when the fifo is full. tudr thir.0 transmit fifo under-run. set when the transmit fifo empties out without the teom control bit being set. an abort is automatically sent. note: the tudr bit is latched and will be cleared when read. thfr: transmit hdlc fifo register (address=b7 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbol position name and description hdlc7 thfr.7 hdlc data bit 7. msb of a hdlc packet data byte. hdlc6 thfr.6 hdlc data bit 6. hdlc5 thfr.5 hdlc data bit 5. hdlc4 thfr.4 hdlc data bit 4. hdlc3 thfr.3 hdlc data bit 3. hdlc2 thfr.2 hdlc data bit 2. hdlc1 thfr.1 hdlc data bit 1. hdlc0 thfr.0 hdlc data bit 0. lsb of a hdlc packet data byte. rdc1: receive hdlc ds0 control register 1 (address=b8 hex) (msb) (lsb) rhs rsads rds0m rd4 rd3 rd2 rd1 rd0 symbol position name and description rhs rdc1.7 receive hdlc source 0 = sa bits defined by rcr2.3 to rcr2.7. 1 = sa bits or ds0 channels define d by rdc1 (see bits defined below). rsads rdc1.6 receive sa bit / ds0 select. 0 = route sa bits to the hdlc cont roller. rd0 to rd4 defines which sa bits are to be routed. rd4 corres ponds to sa4, rd3 to sa5, rd2 to sa6, rd1 to sa7 and rd0 to sa8.
ds21354 & DS21554 67 of 117 symbol position name and description 1 = route ds0 channels into the hd lc controller. rdc1.5 is used to determine how the ds0 channels are selected. rds0m rdc1.5 ds0 selection mode. 0 = utilize the rd0 to rd4 bits to select which single ds0 channel to use. 1 = utilize the rchblk control registers to select which ds0 channels to use. rd4 rdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. rd3 rdc1.3 ds0 channel select bit 3. rd2 rdc1.2 ds0 channel select bit 2. rd1 rdc1.1 ds0 channel select bit 1. rd0 rdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select. rdc2: receive hdlc ds0 control register 2 (address=b9 hex) (msb) (lsb) rdb8 rdb7 rdb6 rdb5 rdb4 rdb3 rdb2 rdb1 symbol position name and description rdb8 rdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to one to stop this bit from being used. rdb7 rdc2.6 ds0 bit 7 suppress enable. set to one to stop this bit from being used. rdb6 rdc2.5 ds0 bit 6 suppress enable. set to one to stop this bit from being used. rdb5 rdc2.4 ds0 bit 5 suppress enable. set to one to stop this bit from being used. rdb4 rdc2.3 ds0 bit 4 suppress enable. set to one to stop this bit from being used. rdb3 rdc2.2 ds0 bit 3 suppress enable. set to one to stop this bit from being used. rdb2 rdc2.1 ds0 bit 2 suppress enable. set to one to stop this bit from being used. rdb1 rdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to one to stop this bit from being used. tdc1: transmit hdlc ds0 control register 1 (address=ba hex) (msb) (lsb) the tsads tds0m td4 td3 td2 td1 td0 symbol position name and description the tdc1.7 transmit hdlc enable. 0 = disable hdlc controller (no data inserted by hdlc controller into the transmit data stream) 1 = enable hdlc controller to allow insertion of hdlc data into either the sa position or multiple ds0 channels as defined by tdc1 (see bit definitions below). tsads tdc1.6 transmit sa bit / ds0 select. this bit is ignored if tdc1.7 is set to zero. 0 = route sa bits from the hdlc controller. td0 to td4 defines which sa bits are to be routed. td4 corres ponds to sa4, td3 to sa5, td2 to sa6, td1 to sa7 and td0 to sa8. 1 = route ds0 channels from the hdlc controller. tdc1.5 is used to determine how the ds0 channels are selected.
ds21354 & DS21554 68 of 117 symbol position name and description tds0m tdc1.5 ds0 selection mode. 0 = utilize the td0 to td4 bits to select which single ds0 channel to use. 1 = utilize the tchblk control registers to select which ds0 channels to use. td4 tdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. td3 tdc1.3 ds0 channel select bit 3. td2 tdc1.2 ds0 channel select bit 2. td1 tdc1.1 ds0 channel select bit 1. td0 tdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select. tdc2: transmit hdlc ds0 control register 2 (address=bb hex) (msb) (lsb) tdb8 tdb7 tdb6 tdb5 tdb4 tdb3 tdb2 tdb1 symbol position name and description tdb8 tdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to one to stop this bit from being used. tdb7 tdc2.6 ds0 bit 7 suppress enable. set to one to stop this bit from being used. tdb6 tdc2.5 ds0 bit 6 suppress enable. set to one to stop this bit from being used. tdb5 tdc2.4 ds0 bit 5 suppress enable. set to one to stop this bit from being used. tdb4 tdc2.3 ds0 bit 4 suppress enable. set to one to stop this bit from being used. tdb3 tdc2.2 ds0 bit 3 suppress enable. set to one to stop this bit from being used. tdb2 tdc2.1 ds0 bit 2 suppress enable. set to one to stop this bit from being used. tdb1 tdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to one to stop this bit from being used. 16 line interface functions the line interface function in the ds21354/554 contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the e1 line, and (3) the jitter attenuator. each of the these three sections is controlled by the line interface control register (licr) which is described below. licr: line interface control register (address=18 hex) (msb) (lsb) l2 l1 l0 egl jas jabds dja tpd symbol position name and description l2 licr.7 line build out select bit 2. sets the transmitter build out; see table 16- 1 and table 16-2. l1 licr.6 line build out select bit 1. sets the transmitter build out; see table 16- 1 and table 16-2. l0 licr.5 line build out select bit 0. sets the transmitter build out; see table 16- 1 and table 16-2. egl licr.4 receive equalizer gain limit. 0 = ?12 db 1 = ?43 db
ds21354 & DS21554 69 of 117 symbol position name and description jas licr.3 jitter attenuator select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side jabds licr.2 jitter attenuator buffer depth select. 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) dja licr.1 disable jitter attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled tpd licr.0 transmit power down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the ttip and tring pins 16.1 receive clock and data recovery the ds21354/554 contains a digital clock recovery sy stem. see figure 3-1 and figure 16-1 for more details. the device couples to the receive e1 shield ed twisted pair or coax via a 1:1 transformer. see table 16-3 for transformer details. the 2.048 mhz cl ock attached at the mclk pin is internally multiplied by 16 via an internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16 times over-sampler which is used to recover the clock and data. this over-sampling technique offers outstanding jitter tolerance (see figure 16-3). normally, the clock that is output at the rclko pin is the recovered clock from the e1 ami/hdb3 waveform presented at the rtip and rring inputs. when no ami signal is present at rtip and rring, a receive carrier loss (rcl) condition will occur and the rclko will be sourced from the clock applied at the mclk pin. if the jitter attenuator is either placed in the transmit path or is disabled, the rclko output can exhibit slightly shorter high cycles of the clock. this is due to the highly over- sampled digital clock recovery circuitr y. if the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the rclk to being close to 50% duty cycle. please see the receive ac timing characteristic s in section 21.3 for more details. 16.2 transmit waveshaping and line driving the ds21354/554 uses a set of laser? trimmed delay lines along with a precision digital?to?analog converter (dac) to create the wave forms that are transmitted onto the e1 line. the waveforms meet the itu g.703 specifications. see figure 16-5. the user will select which waveform is to be generated by properly programming the l2/l1/l0 bits in the line interface control register (licr). the ds21354/554 can set up in a number of various configurations depending on the application. see tables below and figure 16-5.
ds21354 & DS21554 70 of 117 line build out select in licr for the DS21554 table 16 - 1 l2 l1 l0 application transformer retur n loss * rt ** 0 0 0 75 ohm normal 1:1.15 step ? up nm 0 ohms 0 0 1 120 ohm normal 1:1.15 step ? up nm 0 ohms 0 1 0 75 ohm w/ protection resistors 1:1.15 step ? up nm 8.2 ohms 0 1 1 120 ohm w/ protection resistors 1:1.15 step ? up nm 8.2 ohms 1 0 0 75 ohm w/ high return loss 1:1.15 step ? up 21db 27 ohms 1 1 0 75 ohm w/ high return loss 1:1.36 step ? up 21db 18 ohms 1 0 0 120 ohm w/ high return loss 1:1.36 step ? up 21db 27 ohms * nm = not meaningful (return loss value too low for significance) ** see a pplication n ote 324 for details on e1 line interface design line build out select in licr for the ds21354 table 16 - 2 l2 l1 l0 application transformer return loss * rt ** 0 0 0 75 ohm normal 1:2 step ? up nm 0 ohms 0 0 1 120 ohm normal 1:2 step ? up nm 0 oh ms 0 1 0 75 ohm w/ protection resistors 1:2 step ? up nm 2.5 ohms 0 1 1 120 ohm w/ protection resistors 1:2 step ? up nm 2.5 ohms 1 0 0 75 ohm w/ high return loss 1:2 step ? up 21db 6.2 ohms 1 0 1 120 ohm w/ high return loss 1:2 step ? up 21db 11.6 ohms * nm = not meaningful (return loss value too low for significance) ** see a pplication n ote 3 24 for details on e1 line interface design due to the nature of the design of the transmitter in the ds21354/554, very little jitter (less then 0.005 uipp broa dband from 10 hz to 100 khz) is added to the jitter present on tclk. also, the waveform created is independent of the duty cycle of tclk. the transmitter in the device couples to the e1 transmit shielded twisted pair or coax via a 1:1.15 or 1:1.36 step up transformer as shown in figure 16 - 1. in order for the devices to create the proper waveforms, the transformer used must meet the specifications listed in table 16 - 3. the line driver in the device contains a current limiter that will prevent more than 50 m a (rms) from being sourced in a 1 ohm load. transformer specifications table 16 - 3 specification recommended value turns ratio ds21354 1:1(receive) and 1:2(transmit)+/ - 3% turns ratio DS21554 1:1(receive) and 1:1.15 or 1:1.36(transmit)+/ - 3% primary in ductance 600 m h minimum leakage inductance 1.0 m h maximum intertwining capacitance 40 pf maximum dc resistance 1.2 ohms maximum
ds21354 & DS21554 71 of 117 16.3 jitter attenuator the ds21354/554 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the jabds bit in the line interface control register (licr). the 128?bit mode is used in applications where large excursions of wander are expected. the 32?bit mode is used in delay sensitive applications. the characteristics of the attenuation are shown in figure 16-3. the jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the jas bit in the licr. also, the jitter attenuator can be disabled (in effect, removed) by setting the dja bit in the licr. in order for the jitter attenuator to operate properly, a 2.048 mhz cloc k (+/-50 ppm) must be applied at the mclk pin or a crystal with similar characteristics must be applied across the mclk and xtald pins. if a crystal is applied across the mclk and xtald pins, then the maximum effective series resistance should be 30 ohms and capac itors should be placed from each leg of the crystal to ground as shown in figure 16-2. onboard circu itry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the tclki pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/bursty clock at the tclki pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120 uipp (buffer depth is 128 bits) or 28 uipp (buffer depth is 32 bits), then the ds21354/554 will divide the internal nominal 32.768 mhz clock by either 15 or 17 inst ead of the normal 16 to keep the buffer from overflowing. when the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (jalt) bit in the receive information register (rir.5). basic external analog connections figure 16-1 notes: all capacitors values are in uf. 10uf capacitor on tvdd is of tantalum construction. see table 16-1 and table 16-2 for transformer selection. rtip rring ttip tring e1 receive line e1 transmit line ds21354 / 554 0.47 (non- polarized) rr 0.1uf rt rt 1 : 1 n : 1 (see note 1) rr 2.048mhz mclk dvdd dvss 0.1 rvdd rvss 0.1 tvdd tvss 0.1 vdd 0.01 10 +
ds21354 & DS21554 72 of 117 optional crystal connection figure 16-2 jitter tolerance figure 16-3 xtald DS21554/354 c1 c2 2.048 mhz mclk frequency (hz) unit intervals (uipp) 1k 100 10 1 0.1 10 100 1k 10k 100k ds21354/ DS21554 tolerance 1 minimum tolerance level as per itu g.823 40 1.5 0.2 20 2.4k 18k
ds21354 & DS21554 73 of 117 jitter attenuation figure 16-4 transmit waveform template figure 16-5 frequency (hz) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100 k ji t ter att e nuati on c u rv e itu g.7xx prohibited area ets 300 011 & tbr12 prohibited area 40 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ohm systems, 1.0 on the scale = 2.37vpeak in 120 ohm systems, 1.0 on the scale = 3.00vpeak) g.703 template
ds21354 & DS21554 74 of 117 16.4 protected interfaces in certain applications, such as connecting to the pstn, it is required that the network interface be protected from and resistant to certain electrical conditions. these conditions are divided into two categories, surge and power line cross. a typical cause of surge is lightening strike. power line cross refers to accidental contact with high voltage po wer wiring. for protection against surges, additional components and pcb layout considerations are required to reroute and dissipate this energy. in a surge event, the network interface must not be damaged and continue to work after the event. in the event of a power line contact, components such as fuses or ptcs that can ?open? the circuit are required to prevent the possibility of a fire caused by overheating the transformer. the circuit examples in this data sheet are for ?secondary over voltage protection? schemes for the line terminating equipment. primary protection is typically provided by the network service provide and is external to the equipment. figure 16-6 shows an example circuit for the 5 volt device and figure 16-7 is an example for the 3.3 volt device. in both examples, fuses are used to provide protection against power line cross. 470 ohm input resistors on the receive pair, a transient suppresser a nd a diode bridge on the transmit pair provide surge protection. resistors r1 ? r4 provide surge protection for the fuse. careful selection of the transformer will allow the use of a fuse that requires no additional surge protection such as the circuit shown in figure 16-7. the circuit shown in figure 16-7 is required for 3.3 volt operation since additional resistance in the transmit pair cannot be to lerated. for more information on line interface design, consult the e1 line interface design criteria and secondary over voltage protection application notes. these application notes are available from da llas semiconductor? s web site. protected interface example for the DS21554 figure 16-6 note: all capacitor values are in uf. the 10uf capacitor on tvdd is of tantalum construction. the 68uf cap is required to maintain vdd during a transient event. rtip rring ttip tring receive line DS21554 s c1 d1 d2 d3 d4 1:1 fuse fuse transmit line fuse fuse 0.1 n:1 470 470 c2 r1 r2 r3 r4 rt rt rterm rterm x1 x2 +5v 2.048mhz mclk dvdd dvss 0.1 rvdd rvss 0.1 tvdd tvss 0.1 +5.0v 0.01 68 + 10 +
ds21354 & DS21554 75 of 117 componet description d1 ? d4 schottky diode, inte rnational rectifier 11dq04 c1 0.1uf ceramic in para llel with 10uf tantalum c2 .47 uf, non polarized ceramic construction s semtech lc01-6, 6v low capacitance tvs fuse rt rterm r1, r2, r3, r4 x1 x2 for more information on the selection of these components see the separate application notes on secondary over voltage protection and t1 network interface design criteria . these applications notes are available from dallas semiconductor?s web site at www.dalsemi.com protected interface example for the ds21354 figure 16-7 note: all capacitor values are in uf. the 10uf capacitor on tvdd is of tantalum construction. the 68uf cap is required to maintain vdd during a transient event. rtip rring ttip tring receive line ds21354 s c1 d1 d2 d3 d4 1:1 fuse fuse transmit line fuse fuse 0.1 2:1 470 470 c2 37/60 37/60 x1 x2 +3.3v 2.048mhz mclk dvdd dvss 0.1 rvdd rvss 0.1 tvdd tvss 0.1 +3.3v 0.01 68 + 10 +
ds21354 & DS21554 76 of 117 component description d1 ? d4 schottky diode, inte rnational rectifier 11dq04 c1 0.1uf ceramic in para llel with 10uf tantalum c2 .47 uf, non polarized ceramic construction fuse 1.25a slo-blo, littlefuse v2301.25 s semtech lc01-6, 6v low capacitance tvs x1, x2 transpower pt314, low dcr 16.5 receive monitor mode when connecting to a monitor port a large resistive loss is incurred due to the voltage divider between the e1 line termination resistors (rt) and the monitor port isolation resistors (rm) as shown in the figure 16- 8. the receiver of the ds21354/554 can provide gain to overcome the resistive loss of a monitor connection. this is typically a purely resistive loss/ gain and should not be confused with the cable loss characteristics of an e1 transmission line. via the test3 register as shown in the table below, the receiver can be programmed to provide both 12db and 30db of gain. typical monitor port application figure 16-8 receive monitor mode gain table 16-4 test3 (address = ac hex) register value gain 72 hex 12db 70 hex 30db primary e1 terminating device moni tor port jack e1 line x f m r ds21x54 rt rm rm secondary e1 terminating device
ds21354 & DS21554 77 of 117 17 jtag-boundary scan architecture and test access port 17.1 description the ds21354/554 ieee 1149.1 design supports the sta ndard instruction codes sample/preload, bypass, and extest. optional pub lic instructions included are highz, clamp, and idcode. see figure 17-1. the device contains the following as required by ieee 1149.1 standard test access port and boundary scan architecture. test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the ds21354/554 are enhanced versions of the ds2152 and are backward pin-compatible. the jtag feature uses pins that had no function in the ds2152. when using the jtag feature, be sure fms (pin 76) is tied low enabling the newly defined pins of the ds21354/554. details on boundary scan architecture and the test access port can be found in ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. the test access port has the necessary interface pins; jtrst, jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details.
ds21354 & DS21554 78 of 117 jtag functional block diagram figure 17-1 17.2 tap controller state machine the tap controller is a finite state machine that responds to the logic le vel at jtms on the rising edge of jtclk. see figure 17-2. test-logic-reset upon power up, the tap controller will be in the test-l ogic-reset state. the instruction register will contain the idcode instruction. all system logic of the device will operate normally. run-test-idle the run-test-idle is used between scan operations or during specific te sts. the instruction register and test registers will remain idle. select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and will initiate a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir-scan state. +v boundary scan register identi fication register bypass register instruction regi st er jtdi jtms jtclk jtrst jtdo +v +v test access port controller mux 10k 10k 10k sel ect output enabl e
ds21354 & DS21554 79 of 117 capture-dr data may be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of jtclk, the controller will go to the shift- dr state if jtms is low or it will go to the exit1-dr state if jtms is high. shift-dr the test data register selected by the current instruction will be connected between jtdi and jtdo and will shift data one stage towards its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. exit1-dr while in this state, a rising edge on jtclk will put the controller in the update-dr state, which terminates the scanning process, if jtms is high. a rising edge on jtclk with jtms low will put the controller in the pause-dr state. pause-dr shifting of the test registers is halted while in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while jtms is low. a rising edge on jtclk with jtms high will put the controller in the exit2-dr state. exit2-dr a rising edge on jtclk with jtms high while in this state will put the controller in the update-dr state and terminate the scanning process. a rising edge on jtclk with jtms low will enter the shift- dr state. update-dr a falling edge on jtclk while in the update-dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register. select-ir-scan all test registers retain their previous state. the instruction register will remain unchanged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture-ir state and will initiate a scan sequence for the instruction register. jtms high during a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller will enter the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller will enter the shift-ir state.
ds21354 & DS21554 80 of 117 shift-ir in this state, the shift register in the instruction register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk toward s the serial output. the parallel register, as well as all test registers, remain at their previous states. a rising edge on jtclk with jtms high will move the controller to the exit1-ir state. a rising edge on jtclk with jtms low will keep the controller in the shift-ir state while moving data one stage thorough the instruction shift register. exit1-ir a rising edge on jtclk with jtms low will put the controller in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller will enter the update-ir state and terminate the scanning process. pause-ir shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk will put the controller in the exit2-ir state. the cont roller will remain in the pause-ir state if jtms is low during a rising edge on jtclk. exit2-ir a rising edge on jtclk with jtms low will put the controller in the update-ir state. the controller will loop back to shift-ir if jtms is high during a rising edge of jtclk in this state. update-ir the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jtms low, will put the controller in the run-test- idle state. with jtms high, the controller will enter the select-dr-scan state.
ds21354 & DS21554 81 of 117 tap controller state diagram figure 17-2 17.3 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, th e instruction shift register will be connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low will shift the data one stage towards the serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the exit2- ir state with jtms high will move the controller to the update-ir state the falling edge of that same jtclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the ds21354/554 with their respective opera tional binary codes are shown in table 17-1. instruction codes for ieee 1149.1 architecture table 17-1 instruction selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
ds21354 & DS21554 82 of 117 sample/preload this is a mandatory instruction for the ieee 1149.1 specification. this instruction supports two functions. the digital i/os of the device can be samp led at the boundary scan register without interfering with the normal operation of the device by using th e capture-dr state. sample/preload also allows the device to shift data into the boundary scan register via jtdi using the shift-dr state. bypass when the bypass instruction is latched into the parallel instruction register, jtdi connects to jtdo through the one-bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation. extest this allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled via the update-ir state, the parallel outputs of all digital output pins will be driven. the boundary scan register will be connected between jtdi and jtdo. the capture-dr will sample a ll digital inputs into the boundary scan register. clamp all digital outputs of the device w ill output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs will not change during the clamp instruction. highz all digital outputs of the device will be placed in a high impedance state. the bypass register will be connected between jtdi and jtdo. idcode when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code will be loaded into the identification register on the rising edge of jtclk following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially via jtdo. during test-logic-reset, the identification code is forced into the instruction register?s parallel output. the id c ode will always have a ?1? in the lsb position. the next 11 bits identify the manufacturer?s jedec numbe r and number of continuation bytes followed by 16 bits for the device and 4 bits for th e version. see table 17-2. table 17-3 lists the device id codes for the sct devices. id code structure table 17-2 msb lsb version contact factory device id jedec 1 4 bits 16bits 00010100001 1 device id codes table 17-3 device 16-bit id ds21354 0005h DS21554 0003h ds21352 0004h ds21552 0002h
ds21354 & DS21554 83 of 117 17.4 test registers ieee 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. an optional test register has been included with the ds21354/554 design. this test register is the identification register and is used in conjunction with the idcode instruction and the test-logic-reset state of the tap controller. boundary scan register this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells and is n bits in length. see tabl e 17-4 for all of the cell bit locations and definitions. bypass register this is a single one-bit shift register used in conjunction with the bypass, clamp, and highz instructions which provides a s hort path between jtdi and jtdo. identification register the identification register contains a 32-bit shift register and a 32-bit latc hed parallel output. this register is selected during the idcode instruction and when the tap controller is in the test-logic- reset state. see table 17-3 and table 17-4 for more information on bit usage. boundary scan control bits table 17-4 bit pin symbol type control bit description 2 1 rchblk o 2jtmsi 138mclko 4jtclki 5jtrsti 0 6 rcl o 7jtdii 8n/c? 9n/c? 10 jtdo o 72 11 bts i 71 12 liuc i 70 13 8xclk o 69 14 test i 68 15 nc ? 16 rtip i 17 rring i 18 rvdd ? 19 rvss ? 20 rvss ? 21 mclk i 22 xtald o 67 23 nc ? 24 rvss ? 66 25 int o 26 n/c ?
ds21354 & DS21554 84 of 117 bit pin symbol type control bit description 27 n/c ? 28 n/c ? 29 ttip o 30 tvss ? 31 tvdd ? 32 tring o 65 33 tchblk o 64 34 tlclk o 63 35 tlink i 62 36 ci i 61 ? tsync.cntl ? 0 = tsync an input 1 = tsync an output 60 37 tsync i/o 59 38 tposi i 58 39 tnegi i 57 40 tclki i 56 41 tclko o 55 42 tnego o 54 43 tposo o 44 dvdd ? 45 dvss ? 53 46 tclk i 52 47 tser i 51 48 tsig i 50 49 teso o 49 50 tdata i 48 51 tsysclk i 47 52 tssync i 46 53 tchclk o 45 54 co o 44 55 mux i 43 ? bus.cntl ? 0 = d0-d 7/ad0-ad7 are inputs 1 = d0-d7/ad0-ad7 are outputs 42 56 d0/ad0 i/o 41 57 d1/ad1 i/o 40 58 d2/ad2 i/o 39 59 d3/ad3 i/o 60 dvss ? 61 dvdd ? 38 62 d4/ad4 i/o 37 63 d5/ad5 i/o 36 64 d6/ad6 i/o 35 65 d7/ad7 i/o 34 66 a0 i 33 67 a1 i 32 68 a2 i
ds21354 & DS21554 85 of 117 bit pin symbol type control bit description 31 69 a3 i 30 70 a4 i 29 71 a5 i 28 72 a6 i 27 73 ale(as)/a7 i 26 74 rd*(ds*) i 25 75 cs* i 24 76 fms i 23 77 wr*(r/w*) i 22 78 rlink o 21 79 rlclk o 80 dvss ? 81 dvdd 20 82 rclk o 83 dvdd ? 84 dvss ? 19 85 rdata o 18 86 rposi i 17 87 rnegi i 16 88 rclki i 15 89 rclko o 14 90 rnego o 13 91 rposo o 12 92 rchclk o 11 93 rsigf o 10 94 rsig o 995rsero 8 96 rmsync o 7 97 rfsync o 6 ? rsync.cntl ? 0 = rsync an input 1 = rsync an output 5 98 rsync i/o 499rlos/lotco 3 100 rsysclk i
ds21354 & DS21554 86 of 117 18 interleaved pcm bus operation in many architectures, the outputs of individual framers are combined in to higher speed serial buses to simplify transport across the system. the ds21354/554 ca n be configured to a llow data and signaling buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving board space and cost. the interleaved pcm bus option (ibo) supports tw o bus speeds. the 4.096 mhz bus speed allows two scts to share a common bus. the 8.192 mhz bus speed allows four scts to share a common bus. see figure 18-1 for an example of 4 devices sharing a common 8.192mhz pcm bus. each sct that shares a common bus must be configured through software a nd requires the use of one or two device pins. the elastic stores of each sct must be enabled a nd configured for 2.048 mhz operation. see figure 18-1 and table 18-1. for all bus configurations, one sct will be configured as the master device and the remaining scts will be configured as slave devices. in the 4.096 mhz bus c onfiguration there is one master and one slave. in the 8.192 mhz bus configuration there is one master and three slaves. refer to the ibo register description for more detail. ibo: interleave bus operation register (address = b5 hex) (msb) (lsb) - - - - iboen intsel msel0 msel1 symbol position name and description -ibo.6 not assigned . should be set to 0. -ibo.6 not assigned. should be set to 0. -ibo.5 not assigned . should be set to 0. -ibo.4 not assigned . should be set to 0. iboen ibo.3 interleave bus operation enable 0 = interleave bus operation disabled. 1 = interleave bus operation enabled. intsel ibo.2 interleave type select 0 = byte interleave. 1 = frame interleave. msel0 ibo.1 master device bus select bit 0 see table 18-1. msel1 ibo.0 master device bus select bit 1 see table 18-1. ibo master device select table 18-1 msel1 msel0 function 0 0 slave device. 0 1 master device with 1 slave device (4.096 mhz bus rate) 1 0 master device with 3 slav e devices (8.192 mhz bus rate) 11reserved
ds21354 & DS21554 87 of 117 ibo basic configuration using 4 scts figure 18-1 18.1 channel interleave in channel interleave mode data is output to the pcm data out bus one channel at a time from each of the connected scts until all channels of frame n from all each sct has been place on the bus. this mode can be used even when the connect ed scts are operating asynchronous to each other. the elastic stores will manage slip conditions. see figu re 19-11 and figure 19-5 for details. 18.2 frame interleave in frame interleave mode data is output to the pcm data out bus one frame at a time from each of the connected scts. this mode is used only when all connected scts are synchronous. in this mode, slip conditions are not allowed. see figure 19-2 and figure 19-6 for details. rsysclk tsysclk rsync tssync ci co rsig tsig tser rser rsysclk tsysclk ci co rsig tsig tser rser rsysclk tsysclk ci co rsig tsig tser rser rsysclk tsysclk ci co rsig tsig tser rser master sct slave #1 slave #2 salve #3 8.192mhz system clock in system 8khz frame sync in pcm data out pcm data in pcm signaling out pcm signaling in rsync tssync rsync tssync rsync tssync
ds21354 & DS21554 88 of 117 19 functional timing diagrams 19.1 receive receive side timing figure 19-1 notes: 1. rsync in frame mode (rcr1.6 = 0) 2. rsync in multiframe mode (rcr1.6 = 1) 3. rlclk is programmed to output just the sa bits 4. rlink will always output all 5 sa bits as well as the rest of the receive data stream 5. this diagram assumes the cas mf begins in the raf frame frame# 1 23456789101112131415161 4 rli nk rlclk 3 rsync 1 rsync rfsync 2
ds21354 & DS21554 89 of 117 receive side boundary timing (with elastic store disabled) figure 19-2 notes: 1. rchblk is programmed to block channel 1 2. rlclk is programmed to mark the sa4 bit in rlink 3. shown isa rnaf frame boundary 4. rsig normally contains the cas multifra me alignment nibble (0000) in channel 1 channel 32 channel 1 channel 2 channel 32 channel 1 channel 2 rclk rser rsync rfsync rsig rchclk rchblk 1 rlclk rlink 2 cd a lsb msb ab si 1 a sa4 sa5 sa6 sa7 sa8 sa4 sa5 sa6 sa7 sa8 b note 4
ds21354 & DS21554 90 of 117 receive side 1.544 mhz boundary timing (with elastic store enabled) figure 19-3 notes: 1. data from the e1 channels 1. 5. 9, 13, 17, 21, 25, a nd 29 is dropped (channel 2 from the e1 link is (mapped to channel 1 of the t1 link, etc.) and the f-bit position is added (forced to on1) 2. rsync in the output mode (rcr1.5 = 0) 3. rsync in the input mode (rcr1.5 = 1) 4. rchblk is programmed to block channel 24 rser channel 23/31 channel 24/32 channel 1/2 rchclk rchblk rsysclk rsync 2 3 rsync 1 rmsync lsb f msb msb lsb 4
ds21354 & DS21554 91 of 117 receive side 2.048 mhz boundary timing (with elastic store enabled) figure 19-4 notes: 1. rsync is in the output mode (rcr1.5 = 0) 2. rsync is in the input mode (rcr1.5 = 1) 3. rchblk is programmed to block channel 1 4. rsig normally contains the cas multifra me alignment nibble (0000) in channel 1 rser channel 1 rchclk rchblk rsysclk rsync channel 31 channel 32 1 3 rsync 2 rmsync rsig channel 31 channel 32 c d ab channel 1 lsb msb lsb msb c d b a note 4
ds21354 & DS21554 92 of 117 receive side interleave bus operation, byte mode figure 19-5 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. rsync is in the input mode (rcr1.5 = 0). rser lsb sysclk rsync framer 3, channel 32 msb lsb framer 0, channel 1 rsi g framer 3, channel 32 framer 0, channel 1 msb lsb framer 1, channel 1 framer 1, channel 1 3 rser rsync rsi g rser rsi g fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 1 1 2 2 bit detail fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 abcd abcd abcd
ds21354 & DS21554 93 of 117 receive side interleave bus operation, frame mode figure 19-6 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. rsync is in the input mode (rcr1.5 = 0). fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 rser lsb sysclk rsync framer 3, channel 32 msb lsb framer 0, channel 1 rsi g framer 3, channel 32 framer 0, channel 1 msb lsb framer 0, channel 2 framer 0, channel 2 3 rser rsync rsi g rser rsi g 1 1 2 2 bit detail abc/ad/b abc/ad/b abc/ad/b fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32
ds21354 & DS21554 94 of 117 19.2 transmit transmit side timing figure 19-7 notes: 1. tsync in frame mode (tcr1.1 = 0) 2. tsync in multiframe mode (tcr1.1 = 1) 3. tlink is programmed to source just the sa4 bit 4. this diagram assumes both the cas mf and the crc4 mf begin with the taf frame 5. tlink and tlclk are not synchronous with tssync 12345 678910 11 12 1 3 tssync frame# tsync tsync 13 14 15 16 12345 tlclk tlink 14 15 16 678910 3 2
ds21354 & DS21554 95 of 117 transmit side boundary timing (with elastic store disabled) figure 19-8 notes: 1. tsync is in the output mode (tcr1.0 = 1) 2. tsync is in the input mode (tcr1.0 = 0) 3. tchblk is programmed to block channel 2 4. tlink is programmed to source the sa4 bit 5. the signaling data at tsig during channel 1 is normally overwritten in the transmit formatter with the cas mf alignment nibble (0000) 6. shown is a tnaf frame boundary lsb msb lsb msb channel 1 channel 2 channel 1 channel 2 abcd tclk tser tsync tsync tsig tchclk tchblk tlclk tlink 1 2 3 4 don't care si 1 a sa4 sa5 sa6 sa7 sa8 d don't care 4
ds21354 & DS21554 96 of 117 transmit side 1.544 mhz boundary timing (with elastic store enabled) figure 19-9 notes: 1. the f bit position in the tser data is ignored 2. tchblk is programmed to block channel 24 lsb f msb lsb msb channel 1 channel 24 tsysclk tser tssync tchclk tchblk channel 23 1 2
ds21354 & DS21554 97 of 117 transmit side 2.048 mhz boundary timing (with elastic store enabled) figure 19-10 notes: 1. tchblk is programmed to block channel 31 tser lsb msb lsb channel 1 tchclk tchblk tsysclk tssync channel 31 channel 32 notes: 1. tchblk is programmed to block channel 31 tsig dd channel 1 channel 31 channel 32 c b a c b a 1 msb a
ds21354 & DS21554 98 of 117 transmit side interleave bus operation, byte mode figure 19-11 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. tsync is in the input mode (tcr1.0 = 0). tser lsb sysclk tsync framer 3, channel 32 msb lsb framer 0, channel 1 tsig framer 3, channel 32 framer 0, channel 1 msb lsb framer 1, channel 1 framer 1, channel 1 3 tser tsync tsig tser tsig fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 1 1 2 2 bit detail fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 abc/ad/b abc/ad/b abc/ad/b
ds21354 & DS21554 99 of 117 transmit side interleave bus operation, frame mode figure 19-12 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. tsync is in the input mode (tcr1.0 = 0). fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 tser lsb sysclk tsync framer 3, channel 32 msb lsb framer 0, channel 1 tsig framer 3, channel 32 framer 0, channel 1 msb lsb framer 0, channel 2 framer 0, channel 2 3 tser tsync tsig tser tsig 1 1 2 2 bit detail abc/ad/b abc/ad/b abc/ad/b fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32
ds21354 & DS21554 100 of 117 g.802 timing figure 19-13 notes: 1. rchblk or tchblk programmed to pulse high during timeslots 1 through 15, 17 through 25, and bit 1 of timeslot 26 12345678910111213141516171819202122232425262728293031 0 31 32 ts # rsync tsync rchclk tchclk rchblk tchblk channel 26 channel 25 lsb msb rclk / rsysclk tclk / tsysclk rser / tser rchclk / tchclk rchblk / tchblk 12 0
ds21354 & DS21554 101 of 117 ds21354/554 framer synchronization flowchart figure 19-14 fas resync criteria met check for >=915 out of 1000 crc4 word errors 8ms ti me out rlos = 1 set fasrc (rir.1) cas resync criteria met; set casrc (rir.0) fas search fassa = 1 fas sync criteria met fassa = 0 cas sync criteria met cassa = 0 if crc4 is on (ccr1.0 = 1) rlos = 1 if cas is on (ccr1.3 = 0) power up increment crc4 sync counter; crc4sa = 0 crc4 resync crit eri a met (rir.2) cas mul t i f r ame sear ch (if enabled vi a ccr1.3) cassa = 1 crc4 mult iframe search (if enabled vi a ccr1.0) crc4sa = 1 resync i f rcr1. 0 = 0 check for fas framing error (depends on rcr1.2) check for cas mf word error sync decl ared rlos = 0 crc4 sync cri t eri a met ; crc4sa = 0; reset crc4 sync counter
ds21354 & DS21554 102 of 117 ds21354/554 transmit data flow figure 19-15 si bit insertion control (tcr1.3) ti mesl ot 0 pass-through (tcr1.6) e-bi t generati on (tcr2.1) sa bit insertion control (tcr2.3 thru tcr2.7) idle code / channel insertion control via tir1/2/3/4 transmi t unframed all ones (tcr1.4) or auto ais (ccr2.5) code word generation crc4 enable (ccr. 4) taf tnaf.5-7 tlink ts1 to ts16 tidr to waveshapi ng and line driverstpos, 0 1 0 1 1 0 01 1 0 01 01 1 0 ais generation transmit signal ing all ones (tcr1.2) = register = device pin = selector key: tcbr1/2/3/4 rser (note #1) ccr3.6 tcr1.5 signaling bit insertion control tir function select (ccr3.5) ais generation 01 notes: 1. tclk should be tied to rclk and tsync should be tied to rfsync for data to be properly sourced from rser. 2. auto remote alarm i f enabled wil l onl y overwrite bit 3 of timeslot 0 in the not ali gn frames if the alarm needs to be sent. sa bit insertion control register (tsacr) 1 0 tsa4 to tsa8 tra tsinaf tsiaf crc4 mul t i f r ame alignment word generation (ccr.4) receive side crc4 error detector 01 auto remote alarm generation (ccr2.4) per-channel code generation (tcc1/2/3/4) 01 tc1 to tc32 hdlc engine ds0 dat a source mux (tdc1/2) 01 tser & tdata taf/tnaf bit mux 0 1 tnaf.0-4 sa dat a source mux (tdc1) 0 1 ami or hdb3 conver t er ccr1. 6
ds21354 & DS21554 103 of 117 20 operating parameters absolute maximum ratings* voltage on any pin relativ e to ground ?1.0v to +6.0v operating temperature for ds21354l / DS21554l 0 c to 70 c operating temperature for ds21354ln / DS21554ln ?40 c to +85 c storage temperature ?55 c to +125 c soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at th ese or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c; v dd = 3.3v 5% for ds21354l; 0 c to 70 c; v dd = 5.0v 5% for DS21554l; -40 c to +85 c; v dd = 3.3v 5% for ds21354ln; -40 c to +85 c; v dd = 5.0v 5% for DS21554ln) parameter symbol min typ max units notes logic 1 v ih 2.0 5.5 v logic 0 v il ?0.3 +0.8 v supply for ds21354 v dd 3.135 3.3 3.465 v 1 supply for DS21554 v dd 4.75 5 5.25 v 1 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf dc characteristics (0 c to 70 c; v dd = 3.3v 5% for ds21354l; 0 c to 70 c; v dd = 5.0v 5% for DS21554l; -40 c to +85 c; v dd = 3.3v 5% for ds21354ln; -40 c to +85 c; v dd = 5.0v 5% for DS21554ln) parameter symbol min typ max units notes supply current @ 5v i dd 75 ma 2 supply current @ 3.3v i dd 75 ma 2 input leakage i il ?1.0 +1.0 a 3 output leakage i lo 1.0 a 4 output current (2.4v) i oh ?1.0 ma output current (0.4v) i ol +4.0 ma
ds21354 & DS21554 104 of 117 notes: 1. applies to rvdd, tvdd, and dvdd. 2. tclk = tclki = rclki = tsysclk = rs ysclk = mclk = 2.048 mhz; outputs open circuited. 3. 0.0v < v in < v dd . 4. applied to int* when 3?stated. 21 ac timing parameters and diagrams 21.1 multiplexed bus ac characteristics ac characteristics ? multiplexed parallel port (mux = 1) [see figure 21-1 to figure 21-3] (0 c to 70 c; v dd = 3.3v 5% for ds21354l; 0 c to 70 c; v dd = 5.0v 5% for DS21554l; -40 c to +85 c; v dd = 3.3v 5% for ds21354ln; -40 c to +85 c; v dd = 5.0v 5% for DS21554ln) parameter symbol min typ max units notes cycle time t cyc 200 ns pulse width, ds low or rd* high pw el 100 ns pulse width, ds high or rd* low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w* hold time t rwh 10 ns r/w* set up time before ds high t rws 50 ns cs* set up time before ds, wr* or rd* active t cs 20 ns cs* hold time t ch 0ns read data hold time t dhr 10 50 ns write data hold time t dhw 0ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr* or rd* to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr* or rd* t ased 10 ns output data delay time from ds or rd* t ddr 20 80 ns data set up time t dsw 50 ns
ds21354 & DS21554 105 of 117 intel bus read ac timing (bts=0 / mux = 1) figure 21-1 intel bus write timing (bts=0 / mux=1) figure 21-2 ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased cs* a d0-ad7 dhr t ddr ale rd* wr* ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased cs* a d0-ad7 rd* wr* ale
ds21354 & DS21554 106 of 117 motorola bus ac timing (bts = 1 / mux = 1) figure 21-3 t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws ahl pw el t cyc as ds ad0-ad7 (write) ad0-ad7 (read) r/w* cs*
ds21354 & DS21554 107 of 117 21.2 non-multiplexed bus ac characteristics ac characteristics ? non-multiplexed parallel port (mux = 0) [see figure 21-4 to figure 21-7] (0 c to 70 c; v dd = 3.3v 5% for ds21354l; 0 c to 70 c; v dd = 5.0v 5% for DS21554l; -40 c to +85 c; v dd = 3.3v 5% for ds21354ln; -40 c to +85 c; v dd = 5.0v 5% for DS21554ln) parameter symbol min typ max units notes set up time for a0 to a7, valid to cs* active t1 0 ns set up time for cs* active to either rd*, wr*, or ds* active t2 0 ns delay time from either rd* or ds* active to data valid t3 75 ns hold time from either rd*, wr*, or ds* inactive to cs* inactive t4 0 ns hold time from cs* inactive to data bus 3?state t5 5 20 ns wait time from either wr* or ds* active to latch data t6 75 ns data set up time to either wr* or ds* inactive t7 10 ns data hold time from either wr* or ds* inactive t8 10 ns address hold from either wr* or ds* inactive t9 10 ns
ds21354 & DS21554 108 of 117 intel bus read ac timing (bts=0 / mux=0) figure 21-4 intel bus write ac timing (bts=0 / mux=0) figure 21-5 address vali d data valid a0 to a7 d0 to d7 wr* cs* rd* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5 address valid a0 to a7 d0 to d7 rd* cs* wr* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8
ds21354 & DS21554 109 of 117 motorola bus read ac timing (bts=1 / mux=0) figure 21-6 motorola bus write ac timing (bts=1 / mux=0) figure 21-7 address valid data valid a0 to a7 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5 address valid a0 to a7 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8
ds21354 & DS21554 110 of 117 21.3 receive side ac characteristics ac characteristics ? receive side [see figure 21-8 to figure 21-10] (0 c to 70 c; v dd = 3.3v 5% for ds21354l; 0 c to 70 c; v dd = 5.0v 5% for DS21554l; -40 c to +85 c; v dd = 3.3v 5% for ds21354ln; -40 c to +85 c; v dd = 5.0v 5% for DS21554ln) parameter symbol min typ max units notes rclko period t lp 488 ns rclko pulse width t lh t ll 200 200 244 244 ns ns 1 1 rclko pulse width t lh t ll 150 150 244 244 ns ns 2 2 rclki period t cp 488 ns rclki pulse width t ch t cl 75 75 ns ns rsysclk period t sp t sp t sp t sp 100 100 100 100 648 488 244 122 ns ns ns ns 3 4 5 6 rsysclk pulse width t sh t sl 50 50 ns ns rsync set up to rsysclk falling t su 20 t sh ?5 ns rsync pulse width t pw 50 ns rposi/rnegi set up to rclki falling t su 20 ns rposi/rnegi hold from rclki falling t hd 20 ns rsysclk/rclki rise and fall times t r , t f 25 ns delay rclko to rposo, rnego valid t dd 50 ns delay rclk to rser, rdata, rsig, rlink valid t d1 50 ns delay rclk to rchclk, rsync, rchblk, rfsync, rlclk t d2 50 ns delay rsysclk to rser, rsig valid t d3 50 ns delay rsysclk to rchclk, rchblk, rmsync, rsync, co t d4 50 ns ci set up to rsysclk rising t sc 20 ns ci pulse width t wc 50 ns notes: 1. jitter attenuator enabled in the receive path. 2. jitter attenuator disabled or enabled in the transmit path. 3. rsysclk = 1.544 mhz. 4. rsysclk = 2.048 mhz. 5. rsysclk = 4.096 mhz 6. rsysclk = 8.192 mhz
ds21354 & DS21554 111 of 117 receive side ac timing figure 21-8 t d1 1 t d2 t d2 t d2 t d2 rser / rdata / rsig rchclk rchblk rsync rlclk rlink t d1 notes: 1. rsync is in the output mode (rcr1.5 = 0). 2. rlclk will only pulse high during sa bit locations as defined in rcr2; no relationship between rlclk and rsync or rfsync is implied. rclk t d2 rfsync / rmsync msb of channel 1 2 sa4 to sa8 bit position
ds21354 & DS21554 112 of 117 receive system side ac timing figure 21-9 t f t r t d3 1 t d4 t d4 t d4 t t su hd 2 rser / rsig rchclk rchblk rsync rsync notes: 1. rsync is in the output mode (rcr1.5 = 0) 2. rsync is in the input mode (rcr1.5 = 1) rsysclk sl t t sp sh t t d4 rmsync / co msb of channel 1 t sc ci t wc
ds21354 & DS21554 113 of 117 receive line interface ac timing figure 21-10 t f t r rposi , rnegi rclki cl t t cp ch t t su t hd t dd rposo, rnego rclko ll t t lp lh t
ds21354 & DS21554 114 of 117 21.4 transmit ac characteristics ac characteristics ? transmit side [see figure 21-11 to figure 21-13] (0 c to 70 c; v dd = 3.3v 5% for ds21354l; 0 c to 70 c; v dd = 5.0v 5% for DS21554l; -40 c to +85 c; v dd = 3.3v 5% for ds21354ln; -40 c to +85 c; v dd = 5.0v 5% for DS21554ln) parameter symbol min typ max units notes tclk period t cp 488 ns tclk pulse width t ch t cl 75 75 ns ns tclki period t lp 488 ns tclki pulse width t lh t ll 75 75 ns ns tsysclk period t sp t sp t sp t sp 100 100 100 100 648 448 244 122 ns ns ns ns 1 2 3 4 tsysclk pulse width t sh t sl 50 50 ns ns tsync or tssync set up to tclk or tsysclk falling t su 20 t ch ?5 or t sh ?5 ns tsync or tssync pulse width t pw 50 ns tser, tsig, tdata, tlink, tposi, tnegi set up to tclk, tsysclk, tclki falling t su 20 ns tser, tsig, tdata, tlink, tposi, tnegi hold from tclk, tsysclk, tclki falling t hd 20 ns tclk, tclki or tsysclk rise and fall times t r , t f 25 ns delay tclko to tposo, tnego valid t dd 50 ns delay tclk to teso valid t d1 50 ns delay tclk to tchblk, tchclk, tsync, tlclk t d2 50 ns delay tsysclk to tchclk, tchblk, co t d3 75 ns ci set up to tsysclk rising t sc 20 ns ci pulse width t wc 50 ns notes: 1. tsysclk = 1.544 mhz. 2. tsysclk = 2.048 mhz. 3. tsysclk = 4.096 mhz 4. tsysclk = 8.192 mhz
ds21354 & DS21554 115 of 117 transmit side ac timing figure 21-11 t f t r 1 tclk tser / tsig / tdata tchclk t t cl t ch cp tsync tsync tlink tlclk tchblk t d2 t d2 t d2 t t t t t t hd su d2 su hd d1 t hd 2 notes: 1. tsync is in the output mode (tcr1.0 = 1). 2. tsync is in the input mode (tcr1.0 = 0). 3. tser is sampled on the falling edge of tclk when the transmit side elastic store is disabled. 4. tchclk and tchblk are synchronous with tclk when the transmit side elastic store is disabled. 5. tlink is only sampled during sa bit locations as defined in tcr2; no relationship between tlclk/tlink and tsync is implied. 5 teso t su
ds21354 & DS21554 116 of 117 transmit system side ac timing figure 21-12 transmit line interface side ac timing figure 21-13 t f t r tsysclk tser tchclk / co t t sl t sh sp tssync tchblk t d3 t d3 t t t su hd su t hd notes: 1. tser is only sampled on the falling edge of tsysclk when the transmit side elastic store is enabled. 2. tchclk and tchblk are synchronous with tsysclk when the transmit side elastic store is enabled. ci t sc t wc tclko tposo, tnego t dd t f t r tclki tposi, tnegi t t ll t lh lp t hd t su
ds21354 & DS21554 117 of 117 22 mechanical description

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